參數(shù)資料
型號： S29PL032J
廠商： Spansion Inc.
英文描述： CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
中文描述： 3.0伏的CMOS只，同步讀/寫閃存與增強(qiáng)VersatileIO控制記憶
文件頁數(shù)： 69/106頁
文件大?。?/td> 1997K
代理商： S29PL032J
April 7, 200531107A62
S29PL127J/S29PL129J/S29PL064J/S29PL032J
67
P R E L I M I N A R Y
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does
not
require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations.
Table 21
shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the "
Write
Operation Status" section
section for information on these status bits.
Any commands written during the chip erase operation are ignored.
Note that
SecSi Sector, autoselect, and CFI functions are unavailable when a [pro-
gram/erase] operation is in progress.
However, note that a
hardware reset
immediately terminates the erase operation. If that occurs, the chip erase com-
mand sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
5 illustrates the algorithm for the erase operation. Refer to the "
Erase/Program
Operations
" section tables in the AC Characteristics section for parameters, and
Figure 16
section for timing diagrams.
Note:
See
Table 21
for program command sequence.
Figure 4.
Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29PL032J55BAI120 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 32Mbit 2M x 16bit 55ns 48-Pin FBGA Tray 制造商:Spansion 功能描述:FLASH PARALLEL - Trays
S29PL032J55BFI120 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 32MBIT 2MX16 55NS 48FBGA - Trays
S29PL032J60BFI120 制造商:Spansion 功能描述:
S29PL032J60BFI120(E) 制造商:Spansion 功能描述:Cut Tape
S29PL032J70BAI120 功能描述:閃存 32Mb 3V 70ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
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