參數(shù)資料
型號(hào)： S1R72105F00A000
元件分類： 總線控制器
英文描述： SCSI BUS CONTROLLER, PQFP100
封裝： 0.50 MM PITCH, PLASTIC, QFP15-100
文件頁(yè)數(shù)： 61/99頁(yè)
文件大?。?/td> 666K
代理商： S1R72105F00A000
S1R72105 Technical Manual
58
EPSON
Rev.1.0
In Target mode
The CPU issues this command after writing the status byte into SCSI FIFO.
The IC transfers the status in FIFO after setting the status phase.
It sets the GOOD bit of MAININT register and causes an interruption.
In Initiator mode
At the start of execution, negates XSACK if it is asserted.
Enters 1-byte status into SCSI FIFO after checking the status phase at the first timing when XSREQ is asserted.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
The CPU checks the interrupt status and reads the status byte from SCSI FIFO if terminated normally.
Message_In (18H)
Executes the message-in phase.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an
interruption.
In Target mode
The CPU sets the number of bytes of the message to be sent in the NON-DMA data-size register and issues this
command. It writes messages to be transferred into FIFO.
The IC sets the message phase and then sends data equivalent to the number of bytes set in FIFO.
When FIFO is empty, the REQ-ACK handshake is put on hold until when data is accumulated in FIFO.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
Note: Be sure to set the number of bytes of transfer before writing data into FIFO.
In Initiator mode
The CPU sets the number of bytes of the message to be received in the NON-DMA data-size register before
issuing this command.
The IC operates as follows:
At the start of execution, negates XSACK if it is asserted.
Enters the message equivalent to the number of bytes into FIFO after checking the message-in phase at the
timing when REQ is asserted. When FIFO is full, the REQ-ACK handshake is put on hold until when there
is free space available in FIFO.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
Usually, the number of bytes of a message is unknown beforehand. So set the number of transfer to “1” when
the command is issued first and then determine the number of bytes to be received from the second byte by
checking the message code received.
Message_Out (19H)
Executes the message-out phase.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an
interruption.
In Target mode
The CPU sets the number of bytes of the message to be received in the NON-DMA data-size register before
issuing this command.
After setting the message-out phase, the IC enters the message equivalent to the number of bytes set into FIFO.
When FIFO becomes full, the REQ-ACK handshake put on hold until when the CPU reads out the message
from FIFO to make some space available in it.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
Usually, the number of bytes of a message is unknown beforehand. So set the number of transfer to “1” when
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