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| 型號： | S1R72105F00A000 |
| 元件分類： | 總線控制器 |
| 英文描述： | SCSI BUS CONTROLLER, PQFP100 |
| 封裝： | 0.50 MM PITCH, PLASTIC, QFP15-100 |
| 文件頁數(shù)： | 60/99頁 |
| 文件大?。?/td> | 666K |
| 代理商： | S1R72105F00A000 |
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S1R72105 Technical Manual
Rev.1.0
EPSON
57
DMA_Data_In (15H)
Executes the data-in phase between SCSI and buffer.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
Issuing in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption.
In Target mode
Combining this command issued and the AND condition of the DTGO bit of the DMACTL register causes
DMA transfer to be started.
When transfer equivalent to the count value set in the DTBC register is completed, the command is terminated,
the GOOD and DTCMP bits of the MAININT register are set, and an interruption is caused.
In Initiator mode
At the start of execution, negates XSACK if it is asserted.
After the data-out phase is checked at the timing of assertion of XSREQ, the AND condition of the DTGO bit
of the DMACTL register causes actual DMA transfer to start. When a transfer equivalent to the count value
set in the DTBC register is completed, the command is terminated, the GOOD and DTCMP bits of the
MAININT register are set, and an interruption is caused.
If any other phase is found when the data-in phase is checked, the IC sets ILPHS of SCSIINT1 and causes an
interruption.
Non-DMA_Data_In (16H)
Valid only when the command is connected, which executes the data-in phase between SCSI and CPU interface.
It can be issued in either Target or Initiator mode.
Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an
interruption.
In Target mode
Sets the number of transfer in the NON-DMA data-size register and issues this command.
The CPU writes data into FIFO by check the status of FIFO.
The IC operates as follows:
Outputs data equivalent to the number of bytes set from FIFO after setting the data-in phase.
When FIFO is empty, the REQ-ACK handshake is put on hold until when data is accumulated in FIFO.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
Note: Be sure to set the number of bytes of transfer before writing data into FIFO.
In Initiator mode
Sets the number of transfer in the NON-DMA data-size register and issues this command.
The CPU reads data from FIFO by checking the status of FIFO.
The IC operates as follows:
At the start of execution, negates XSACK if it is asserted.
Enters data into FIFO after checking the data-in phase at the timing of assertion of XSREQ.
When FIFO is full, the REQ-ACK handshake is put on hold until when there is free space available in FIFO.
If any other phase is found when the data-in phase is checked, the IC sets ILPHS of SCSIINT1 and causes an
interruption.
Status_In (17H)
Executes the status phase.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an
interruption.
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