參數(shù)資料
型號(hào)： S1R72105F00A000
元件分類： 總線控制器
英文描述： SCSI BUS CONTROLLER, PQFP100
封裝： 0.50 MM PITCH, PLASTIC, QFP15-100
文件頁數(shù)： 33/99頁
文件大?。?/td> 666K
代理商： S1R72105F00A000
S1R72105 Technical Manual
Rev.1.0
EPSON
33
7.3.32
SCSI Mode Select1 (SCSIMODE1)
R/W
Sets operation related to the SCSI interface.
Address
Register Name
Bit Symbol
Description
2Ah
SCSIMODE1
7: STPPE
STOP BY PARITY ERROR
6: ATNPE
ATN ASSERT BY PARITY ERROR
5: STATN
STOP BY ATN ASSERT
4: AUTO
AUTO SEND STATUS/MESSAGE
3: RINH
RESELECTION INHIBIT
2: SINH
SELECTION INHIBIT
1: DIRECT
SCSI DIRECT ACCESS ENABLE
0: SPCEN
SCSI PARITY CHECK ENABLE
BIT7 STOP BY PARITY ERROR
When this bit is HIGH it suspends the SCSI control command in process of execution if a parity error is detected on
the SCSI interface.
BIT6 ATN ASSERT BY PARITY ERROR
When this bit is HIGH it asserts a target device ATN if a parity error is detected on the SCSI interface. Any setting
of this bit becomes invalid when the SCSI parity check is disabled.
This bit is valid only in Initiator mode.
BIT5 STOP BY ATN ASSERT
When this bit is HIGH it suspends the SCSI control command in process of execution if assertion of ATN is detected.
This bit is valid only in Target mode.
BIT4 AUTO SEND STATUS/MESSAGE
When this bit is HIGH it puts the SCSI control command “Status_Message” into Automatic Transmission mode. In
this mode, the FLAG and LINK bits of the SCSI command block which have been received are checked. When the
LINK bit is LOW status 00h(GOOD) and message 00h(COMMAND COMPLETE) are automatically sent. When the
LINK bit is LOW status 10h(INTERMEDIATE GOOD) and message 0Ah(LINKED COMMAND COMPLETE) are
automatically sent. When both LINK bit and FLAG bit are HIGH status 10h(INTERMEDIATE GOOD) and
message 0Bh(LINKED COMMAND COMPLETE WITH FLAG) are automatically sent.
BIT3 RESELECTION INHIBIT
When this bit is HIGH it disables response to re-selection.
BIT2 SELECTION INHIBIT
When this bit is HIGH it disables response to selection.
BIT1 SCSI DIRECT ACCESS ENABLE
When this bit is set to HIGH SCSI signal lines of this bit can be directly controlled from the CPU by using the SCSI
data register and SCSI control register. The status of the signal lines can always be monitored regardless of the status
of this bit.
BIT0 SCSI PARITY CHECK ENABLE
When this bit is HIGH parity check of the SCSI data bus is performed during the selection phase (when it is selected)
and when data from SCSI is input.
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