參數(shù)資料
型號(hào)： S1R72105F00A000
元件分類： 總線控制器
英文描述： SCSI BUS CONTROLLER, PQFP100
封裝： 0.50 MM PITCH, PLASTIC, QFP15-100
文件頁(yè)數(shù)： 44/99頁(yè)
文件大?。?/td> 666K
代理商： S1R72105F00A000
S1R72105 Technical Manual
Rev.1.0
EPSON
43
7.5.2.3
EP0 In Transaction Control (EP0InControl)
R/W
Sets operation to IN Transaction.
USBIndex : 00h
Address
Register Name
Bit Symbol
Description
1Ah
EP0InControl
7: InForceNAK
IN Transaction Force NAK
6: InForceSTALL
IN Transaction Force STALL
5: InEnShortPkt
IN Transaction Short Packet Enable
4: 0
Reserved
3: 0
Reserved
2: InToggleStat
IN Transaction Toggle Status
1: InToggleClr
IN Transaction Toggle Clear
0: InToggleSet
IN Transaction Toggle Set
BIT7 IN Transaction Force NAK
Setting this bit to HIGH returns NAK to IN Transaction.
When the RcvEP0SETUP bit of the MainIntStat register is set to HIGH as a result of completing the SETUP stage, this
bit is set to HIGH while the RcvEP0SETUP bit is HIGH. Therefore, the RcvEP0SETUP bit must be cleared to LOW
to clear this bit to LOW.
If the direction of transfer of data stage is IN, the data stage can be executed by clearing this bit to LOW after setting
the direction by the OUTxIN bit of the EP0Config_1 register.
If the direction of transfer of data stage is OUT, the data stage can be executed by clearing this bit to LOW after the
status stage is ready.
When there is a transaction that is being executed, setting of this bit a fixed period of time after starting transaction
becomes valid from the next transaction.
BIT6 IN Transaction Force STALL
When this bit is set to HIGH it becomes valid, taking precedence over the setting of the INForceNAK bit.
Setting this bit to HIGH returns STALL to IN Transaction.
When the RcvEP0SETUP bit of the MainIntStat register is set to HIGH as a result of completing the SETUP stage, this
bit is set to LOW while the RcvEP0SETUP bit is HIGH. Therefore, the RcvEP0SETUP bit must be cleared to LOW
to set this bit to HIGH.
When there is a transaction that is being executed, setting of this bit a fixed period of time after starting transaction
becomes valid from the next transaction.
BIT5 IN Transaction Short Packet Enable
Setting this bit to HIGH returns data packet to IN Transaction independent of amount of data of FIFO.
When packet transfer is completed after setting this bit to HIGH this bit returns to LOW.
BIT2 IN Transaction Toggle Status
Shows the state of Toggle Sequence bit during IN Transaction.
It is set to 1 when SETUP Token is received.
BIT1 IN Transaction Toggle Clear
Clears the Toggle Sequence bit during IN Transaction to 0.
BIT0 IN Transaction Toggle Set
Sets the Toggle Sequence bit during IN Transaction to 1.
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