參數(shù)資料
型號: S1R72105F00A000
元件分類: 總線控制器
英文描述: SCSI BUS CONTROLLER, PQFP100
封裝: 0.50 MM PITCH, PLASTIC, QFP15-100
文件頁數(shù): 43/99頁
文件大?。?/td> 666K
代理商: S1R72105F00A000
S1R72105 Technical Manual
42
EPSON
Rev.1.0
7.5.2
Description of Registers by Set Value of USBIndex
7.5.2.1
USB Address (USBAddress)
R/W
Sets the USB Address.
This setting is cleared (set 00h) when the USB BusReset is detected.
USBIndex : 00h
Address
Register Name
Bit Symbol
Description
18h
USBAddress
7: 0
Reserved
6: USBAddress[6]
5: USBAddress[5]
4: USBAddress[4]
3: USBAddress[3]
USB Address
2: USBAddress[2]
1: USBAddress[1]
0: USBAddress[0]
BIT7 RESERVED
BIT6-0
Sets the USB Address.
This setting is cleared (set 00h) when the USB BusReset is detected.
Set the address specified by the host when control transfer of the SetAddress request is completed.
7.5.2.2
EP0 Config 1 (EP0Config_1)
R/W
Sets operation of the Endpoint 0.
USBIndex : 00h
Address
Register Name
Bit Symbol
Description
19h
EP0Config_1
7: OUT
× IN
OUT
× IN
6: 0
Reserved
5: 0
Reserved
4: 0
Reserved
3: MaxPacketSize[3]
2: MaxPacketSize[2]
Max Packet Size
1: MaxPacketSize[1]
0: MaxPacketSize[0]
BIT7 OUT
× IN
Sets the direction of transfer of Endpoint 0.
Set the direction of transfer in data stage by interpreting the request in SETUP stage.
After completion of setting of the direction of the data stage, it can be executed by clearing the InForceNAK bit or
OutForceNAK bit to LOW in either of the EP0InControl or EP0OutControl register, which controls the direction of
data stage.
0: IN direction
1: OUT direction
BIT3-0 Max Packet Size
Sets MaxPacketSize of Endpoint 0.
The list corresponding to these bits is as follows:
After setting this field, AllFIFOClr in the EP0FIFOCtrl register must be set to HIGH once.
(bit3, bit2, bit1, bit0)
0
1
: 8 bytes
0
1
0
: 16 bytes
0
: 32 bytes
1
0
: 64 bytes
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