參數(shù)資料
型號(hào)： S1R72105F00A000
元件分類： 總線控制器
英文描述： SCSI BUS CONTROLLER, PQFP100
封裝： 0.50 MM PITCH, PLASTIC, QFP15-100
文件頁(yè)數(shù)： 20/99頁(yè)
文件大?。?/td> 666K
代理商： S1R72105F00A000
S1R72105 Technical Manual
Rev.1.0
EPSON
21
7.3.10
System Control(SystemCtrl)
R/W
Sets the system operation.
Address
Register Name
Bit Symbol
Description
09h
SystemCtrl
7: 0
Reserved
6: 0
Reserved
5: 0
Reserved
4: GoSuspend
Go Suspend
3: SendWakeup
Send Wakeup
2: 0
Reserved
1: xINTmode 1
xINT Mode 1
0: xINTmode 0
xINT Mode 0
BIT4 Go Suspend
Setting this bit to HIGH places this IC in the Suspend mode.
The clock supplying to internal circuits and external elements does not stop.
This bit is used only for enabling USB Resume interrupt.
BIT3 Send Wakeup
Setting this bit to HIGH restores to the previous state from the Suspend state.
BIT1 xINT Mode1
Determines the operation mode of the XINTU signal.
0: Outputs LOW when asserting interrupt and HIGH when negating it.
1: Outputs LOW when asserting interrupt and becomes “Hi-Z” condition when negating it.
BIT0 xINT Mode0
Determines the operation mode of the XINTS signal.
0: Outputs LOW when asserting interrupt and HIGH when negating it.
1: Outputs LOW when asserting interrupt and becomes “Hi-Z” condition when negating it.
7.3.11
USB Common(USBCommon)
R/W
Sets operation of the USB interface.
Address
Register Name
Bit Symbol
Description
0Ah
USBCommont
7: VBUS
VBUS
6: 0
Reserved
5: 0
Reserved
4: 0
Reserved
3: 0
Reserved
2: IgnrTglMis
Ignore Toggle Mismatch
1: EnPullUp
Enable Pull Up
0: ActiveUSB
Active USB Interface
BIT7 VBUS
Shows the state of the VBUS signal.
0: Disconnected state (VBUS = LOW)
1: Connected state (VBUS = HIGH)
BIT2 IgnrTglMis
Sets the operation mode at the time of toggle mismatch in Out transaction.
0: Asserts the OUTransACK status of the relevant endpoint at the time of toggle mismatch.
1: Does not assert the OUTransACK status of the relevant endpoint at the time of toggle mismatch.
BIT1 Enable Pull Up
The XPUENB pin becomes LOW by setting this bit to HIGH after checking the state of connection of the VBUS signal.
Effective when pull up control of the USB bus is performed by XPUENB.
Combining 5V input of VBUS and the AND condition of this bit causes the XPUENB pin to become LOW.
BIT0 Active USB Interface
After resetting, the USB interface ignores all packets until this bit is set.
It activates by setting this bit to HIGH after completion of initialization.
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