參數(shù)資料
型號(hào): S1R72105F00A000
元件分類: 總線控制器
英文描述: SCSI BUS CONTROLLER, PQFP100
封裝: 0.50 MM PITCH, PLASTIC, QFP15-100
文件頁數(shù): 5/99頁
文件大?。?/td> 666K
代理商: S1R72105F00A000
S1R72105 Technical Manual
Rev.1.0
EPSON
7
6.6
USB Interface Circuit
(1) It supports full speed device in conformity to the USB1.1 (It does not support low speed).
It supports control transfer (endpoint 0), bulk transfer, and interrupt transfer (It does not support
isochronous transfer).
(2) Split of the built-in SRAM (256 bytes) is programmable by user definition.
In addition to two-way endpoint 0, a maximum of three endpoints can be set.
Three endpoints can be independently set to IN/OUT direction, any of four maximum packet lengths (8, 16,
32 or 64 bytes), any endpoint number, and buffer size (single or double).
6.7
PLL Circuit (Internal System Clock Generating Section)
This IC has the function to generate 40MHz(SCSI) and 48MHz(USB) required for the internal circuit from the
clock generated by the oscillation circuit by using the PLL circuit.
The block diagram around the oscillation section is shown below:
The IC enables easy setup of an oscillation circuit by connecting a crystal vibrator and feedback resistor
(For characteristics of the crystal vibrator, contact us separately).
It allows oscillation of 20MHz by means of the oscillation circuit mentioned above.
In this case, 40MHz and 48MHz required for each block of SCSI and USB are generated by using the
internal PLL. So connect the EXCLK pin to LVDD or GND (CLKSEL = LVDD).
The IC allows operation by inputting a 40MHz external clock of 3.3V level to the OSCIN pin or 40MHz
oscillation and inputting a 48MHz external clock of 3.3V level to the EXCLK pin without using the
internal PLL. In this case, connect the CLKSEL to the “GND” to stop operation of the PLL block.
PLL
LVDD or GND
VC
4.7k
100pF
GND
(20MHz/40MHz)
OSCOUT
5pF
GND
5pF
GND
OSCIN
1M
EXCLK
B(0)
Y
A(1)
S
B(0)
Y
A(1)
S
SCSI
40MHz
USB
48MHz
GND
3pF
CLKSEL
Internal clock
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