參數資料
型號： RM7065A
廠商： PMC-SIERRA INC
元件分類： 微控制器/微處理器
英文描述： 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
中文描述： 64-BIT, 400 MHz, RISC PROCESSOR, PBGA256
封裝： 27 X 27 MM, TBGA-256
文件頁數： 5/52頁
文件大?。?/td> 776K
代理商： RM7065A
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
5
Table of Contents
1
2
3
4
Features ..................................................................................................................................9
Block Diagram .......................................................................................................................10
Description ............................................................................................................................11
Hardware Overview ...............................................................................................................12
4.1
CPU Registers .............................................................................................................12
4.2
Superscalar Dispatch ...................................................................................................12
4.3
Pipeline ........................................................................................................................13
4.4
Integer Unit ..................................................................................................................14
4.5
ALU ..............................................................................................................................15
4.6
Integer Multiply/Divide ..................................................................................................15
4.7
Floating-Point Coprocessor ..........................................................................................16
4.8
Floating-Point Unit .......................................................................................................16
4.9
Floating-Point General Register File ............................................................................17
4.10 System Control Coprocessor (CP0) .............................................................................18
4.11 System Control Coprocessor Registers .......................................................................18
4.12 Virtual to Physical Address Mapping ............................................................................19
4.13 Joint TLB ......................................................................................................................20
4.14 Instruction TLB .............................................................................................................21
4.15 Data TLB ......................................................................................................................21
4.16 Cache Memory .............................................................................................................22
4.17 Instruction Cache .........................................................................................................22
4.18 Data Cache ..................................................................................................................22
4.19 Secondary Cache ........................................................................................................24
4.20 Secondary Caching Protocols ......................................................................................24
4.21 Cache Locking .............................................................................................................25
4.22 Cache Management .....................................................................................................26
4.23 Primary Write Buffer .....................................................................................................26
4.24 System Interface ..........................................................................................................26
4.25 System Address/Data Bus ...........................................................................................27
4.26 System Command Bus ................................................................................................27
4.27 Handshake Signals ......................................................................................................28
4.28 System Interface Operation .........................................................................................28
4.29 Data Prefetch ...............................................................................................................30
4.30 Enhanced Write Modes ................................................................................................31
4.31 External Requests ........................................................................................................31
4.32 Test/Breakpoint Registers ............................................................................................31
4.33 Performance Counters .................................................................................................32
4.34 Interrupt Handling ........................................................................................................34
4.35 Standby Mode ..............................................................................................................36
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