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參數(shù)資料
| 型號： | RM7065A |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| 中文描述： | 64-BIT, 400 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 27 X 27 MM, TBGA-256 |
| 文件頁數(shù)： | 39/52頁 |
| 文件大小： | 776K |
| 代理商： | RM7065A |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
39
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Table 18
Clock/Control Interface
Pin Name
SysClock
SysADC(7:0)
Input/Output
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data
cycles.
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the
processor and an external agent.
System Command/Data Identifier Bus Parity
For the RM7065A, unused on input and zero on output.
SysCmd(8:0)
Input/Output
SysCmdP
Input/Output
Type
Input
Description
System clock
Master clock input used as the system interface reference clock. All
output timings are relative to this input clock. Pipeline operation
frequency is derived by multiplying this clock up by the factor selected
during boot initialization
Vcc for PLL
Quiet VccInt for the internal phase locked loop. Must be connected to
VccInt through a filter circuit.
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to
VssInt through a filter circuit.
VccP
Input
VssP
Input
Pin Name
Type
Description
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