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參數(shù)資料
| 型號(hào)： | RM7065A |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| 中文描述： | 64-BIT, 400 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 27 X 27 MM, TBGA-256 |
| 文件頁數(shù)： | 40/52頁 |
| 文件大?。?/td> | 776K |
| 代理商： | RM7065A |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
40
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Table 19
Interrupt Interface
Pin Name
IP*(9:0)
Table 20
JTAG Interface
Pin Name
JTDI
Table 21
Initialization Interface
Pin Name
BigEndian
Type
Input
Description
Interrupt
Ten general processor interrupts, bit-wise ORed with bits 9:0 of the
interrupt register.
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 15 of the interrupt register (bit 6
in R5000 compatibility mode).
NMI*
Input
Type
Input
Description
JTAG data in
JTAG serial data in.
JTAG clock input
JTAG serial clock input.
JTAG data out
JTAG serial data out.
JTAG command
JTAG command signal, signals that the incoming serial data is
command data.
JTCK
Input
JTDO
Output
JTMS
Input
Type
Input
Description
Big Endian / Little Endian Control
Allows the system to change the processor addressing mode without
rewriting the mode ROM.
Vcc is OK
When asserted, this signal indicates to the RM7065A that the VccInt
power supply has been above the recommended value for more than
100 milliseconds and will remain stable. The assertion of VccOK
initiates the reading of the boot-time mode control serial stream.
Cold Reset
This signal must be asserted for a power on reset or a cold reset.
ColdReset must be de-asserted synchronously with SysClock.
Reset
This signal must be asserted for any reset sequence. It may be
asserted synchronously or asynchronously for a cold reset, or
synchronously to initiate a warm reset. Reset must be de-asserted
synchronously with SysClock.
Boot Mode Clock
Serial boot-mode data clock output at the system clock frequency
divided by two hundred and fifty six.
Boot Mode Data In
Serial boot-mode data input.
VccOK
Input
ColdReset*
Input
Reset*
Input
ModeClock
Output
ModeIn
Input
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