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參數(shù)資料
| 型號： | RM7065A |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| 中文描述： | 64-BIT, 400 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 27 X 27 MM, TBGA-256 |
| 文件頁數(shù)： | 15/52頁 |
| 文件大?。?/td> | 776K |
| 代理商： | RM7065A |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
15
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
4.5
ALU
The RM7065A has two complete integer ALUs each consisting of an integer adder/subtractor, a
logic unit, and a shifter. Table 3 shows the functions performed by the ALUs for each execution
unit. Each of these units is optimized to perform all operations in a single processor cycle.
Table 3 ALU Operations
Unit
F Pipe
Adder
add, sub
4.6
Integer Multiply/Divide
The RM7065A has a single dedicated integer multiply/divide unit optimized for high-speed
multiply and multiply-accumulate operations. The multiply/divide unit resides in the F type
execution unit. Table 4 shows the performance of the multiply/divide unit on each operation.
Table 4 Integer Multiply/Divide Operations
Operand
Size
16 bit
32 bit
16 bit
32 bit
DMULT,
DMULTU
DIV, DIVD
any
DDIV,
DDIVU
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in
the Hi and Lo registers. These values can then be transferred to the general purpose register file
using the Move-from-Hi and Move-from-Lo (
MFHI
/
MFLO
) instructions.
In addition to the baseline MIPS IV integer multiply instructions, the RM7065A also implements
the 3-operand multiply instruction,
MUL
. This instruction specifies that the multiply result go
directly to the integer register file rather than the Lo register. The portion of the multiply that
would have normally gone into the Hi register is discarded. For applications where it is known that
the upper half of the multiply result is not required, using the
MUL
instruction eliminates the
necessity of executing an explicit
MFLO
instruction.
The multiply-add instructions,
MAD
and
MADU
, multiply two operands and add the resulting
product to the current contents of the Hi and Lo registers. The multiply-accumulate operation is
M Pipe
add, sub, data address
add
logic, moves, zero shifts
(nop)
non zero shift, store
align
Logic
logic, moves, zero shifts
(nop)
non zero shift
Shifter
Opcode
Latency
Repeat
Rate
Stall
Cycles
MULT/U,
MAD/U
4
5
4
5
9
3
4
3
4
8
0
0
2
3
0
MUL
any
36
68
36
68
0
0
any
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