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參數(shù)資料
| 型號(hào)： | RM7065A |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| 中文描述： | 64-BIT, 400 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 27 X 27 MM, TBGA-256 |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 776K |
| 代理商： | RM7065A |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
30
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Figure 9 Processor Block Write
Figure 10 Multiple Outstanding Reads
4.29 Data Prefetch
The RM7065A is the first PMC-Sierra design to support the MIPS IV integer data prefetch
(
PREF
) and floating-point data prefetch (
PREFX
) instructions. These instructions are used by
the compiler or by an assembly language programmer when it is known or suspected that an
upcoming data reference is going to miss in the cache. By appropriately placing a prefetch
instruction, the memory latency can be hidden under the execution of other instructions. In cases
where the execution of a prefetch instruction would cause a memory management or address error
exception the prefetch is treated as a
NOP
.
The
“
Hint
”
field of the data prefetch instruction is used to specify the action taken by the
instruction. The instruction can operate normally (that is, fetching data as if for a load operation) or
it can allocate and fill a cache line with zeroes on a primary data cache miss.
SysClock
SysAD
Addr
Data0
Data1
Data2
Data3
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Write
NData
NData
NData
NEOD
PRqst*
PAck*
Release*
SysClock
SysAD
SysCmd
ValidOut*
ValidIn*
Addr
1
Data1
Data1
Read
1
Data0
Addr
2
Data0
Data0
2
Read
2
NData
Master
Processor
Processor
Processor
Processor
Data1
2
NData
System
System
RspSwap*
2
3
4
5
6
7
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