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參數(shù)資料
| 型號： | RM7065A |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| 中文描述： | 64-BIT, 400 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 27 X 27 MM, TBGA-256 |
| 文件頁數(shù)： | 32/52頁 |
| 文件大?。?/td> | 776K |
| 代理商： | RM7065A |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
32
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Table 9 Watch Control Register
Register
Bit Field/Function
63
Watch1, 2
Store
Note that the
W1
and
W2
bits of the Cause register indicate which Watch register caused a partic-
ular Watch exception.
4.33 Performance Counters
To facilitate system tuning, the RM7065A implements a performance counter using two new CP0
registers, PerfCount and PerfControl. The PerfCount register is a 32-bit writable counter which
causes an interrupt when bit 31 is set. The PerfControl register is a 32-bit register containing a 5-
bit field which selects one of twenty-two event types as well as a handful of bits which control the
overall counting function. Note that only one event type can be counted at a time and that counting
can occur for user code, kernel code, or both. The event types and control bits are listed in Table
10.
62
Load
61
Instr
60:36
0
35:2
Addr
1
Mask
Watch
2
1:0
0
0
Mask
Watch
1
31:2
Mask
Watch Mask
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