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| 型號(hào)： | RM7065A |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| 中文描述： | 64-BIT, 400 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 27 X 27 MM, TBGA-256 |
| 文件頁(yè)數(shù)： | 29/52頁(yè) |
| 文件大?。?/td> | 776K |
| 代理商： | RM7065A |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
29
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Figure 8 Processor Block Read
In Figure 8 the read latency is 4 cycles (
ValidOut*
to
ValidIn*
), and the response data pattern is
DDxxDD. Figure 9 shows a processor block write where the processor was programmed with
write-back data rate boot code 2, or DDxxDDxx.
Finally, Figure 10 shows a typical sequence resulting in two outstanding reads, as explained in the
following sequence.
1. The processor issues a read.
2. The external agent takes control of the bus in preparation for returning data to the processor.
3. The processor encounters another internal cache miss and therefore asserts
PRqst*
in order to
regain control of the bus.
4. The external agent pulses
PAck*
, returning control of the bus to the processor.
5. The processor issues a read for the second miss.
6. The
RspSwap*
pin is asserted to denote the out of order response. Not shown in the figure is
the completion of the data transfer for the second miss, or any of the data transfer for the first
miss.
7. The external agent retakes control of the bus and begins returning data (out of order) for the
second miss to the processor
SysClock
SysAD
Addr
Data0
Data1
Data2
Data3
SysCmd
Read
NData
NData
NData
NEOD
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
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