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參數(shù)資料
| 型號： | RM5231A-250-H |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| 中文描述： | 64-BIT, 250 MHz, MICROPROCESSOR, PQFP128 |
| 封裝： | MQFP-128 |
| 文件頁數(shù)： | 35/40頁 |
| 文件大?。?/td> | 595K |
| 代理商： | RM5231A-250-H |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
35
RM5231A Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
9.3
System Interface Parameters
1
9.4
Boot-Time Interface Parameters
CPU Speed
250 MHz to 350 MHz
Parameter
1
Symbol Conditions
t
DO
mode14..13 = 10
5,6
(fastest)
Min
1.0
Max
5.0
Units
ns
Data Output
2,3
mode14..13 = 01
5,6
(slowest)
t
rise
= see above table
t
fall
= see above table
1.0
6.0
ns
Data Setup
4
t
DS6
t
DH
2.5
ns
Data Hold
4
Notes
1.
Timings are measured from 0.425 x VccIO
of clock to 0.425 x VccIO of signal for 3.3V I/O. Timings are
measured from 0.48 x VccIO of clock to 0.48
x
VccIO of signal for
2.5V I/O.
2.
Capacitive load for all maximum output timings is 50 pF. Minimum output timings are for theoretical no load
condition-untested.
3.
Data Output timing applies to all signal pins whether tristate I/O or output only.
4.
Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5.
Only mode 14:13 = 10 is tested and guaranteed.
6.
Data shown is for 3.3 V I/O. For 2.5 V I/O derate all times by .5 nS.
1.0
ns
Parameter
Mode Data Setup
Symbol
t
DS
t
DH
Min
4
Max
Units
SysClock cycles
Mode Data Hold
0
SysClock cycles
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM5231A-300-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-300-HI | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-350-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5261A | RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary |
| RM5261A-250-H | RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary |
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