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參數(shù)資料
| 型號： | RM5231A-250-H |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| 中文描述： | 64-BIT, 250 MHz, MICROPROCESSOR, PQFP128 |
| 封裝： | MQFP-128 |
| 文件頁數(shù)： | 15/40頁 |
| 文件大小： | 595K |
| 代理商： | RM5231A-250-H |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
15
RM5231A Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Table 2 Floating-Point Instruction Cycles
Operation
fadd
fsub
fmult
fmadd
fmsub
fdiv
fsqrt
frecip
frsqrt
fcvt.s.d
fcvt.s.w
fcvt.s.l
fcvt.d.s
fcvt.d.w
fcvt.d.l
fcvt.w.s
fcvt.w.d
fcvt.l.s
fcvt.l.d
fcmp
fmov
fmovc
fabs
fneg
Note
1.
Numbers are represented as single/double precision format.
3.10 Floating-Point General Register File
The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. With the
floating-point load and store double instructions (
LDC1
and
SDC1
), the floating-point unit can
take advantage of the 64-bit wide data cache and issue a floating-point co-processor load or store
doubleword instruction in every cycle.
The floating-point control register space contains two registers; one for determining configuration
and revision information for the coprocessor and one for control and status information. These are
primarily used for diagnostic software, exception handling, state saving and restoring, and control
of rounding modes. To support superscalar operation, the FGR has four read ports and two write
ports, and is fully bypassed to minimize operation latency in the pipeline. Three of the read ports
and one write port are used to support the combined multiply-add instruction while the fourth read
and second write port allows a concurrent floating-point load or store.
Latency
4
4
4/5
4/5
4/5
21/36
21/36
21/36
38/68
4
6
6
4
4
4
4
4
4
4
1
1
1
1
1
Repeat Rate
1
1
1/2
1/2
1/2
19/34
19/34
19/34
36/66
1
3
3
1
1
1
1
1
1
1
1
1
1
1
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM5231A-300-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-300-HI | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-350-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5261A | RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary |
| RM5261A-250-H | RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM525A-R2 | 制造商:Black Box Corporation 功能描述:2U Wallmount Cabinet, Beige |
| RM5260-133Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5260-150Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5260-175Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5260-200Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
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