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參數(shù)資料
| 型號： | RM5231A-250-H |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| 中文描述： | 64-BIT, 250 MHz, MICROPROCESSOR, PQFP128 |
| 封裝： | MQFP-128 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 595K |
| 代理商： | RM5231A-250-H |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
18
RM5231A Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Figure 5 shows the address space layout for 32-bit operation.
Figure 5 Kernel Mode Virtual Addressing (32-bit)
Kernel virtual address space
(kseg3)
Mapped, 0.5GB
0xE0000000
Supervisor virtual address space
(ksseg)
Mapped, 0.5GB
0xC0000000
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
0xA0000000
Cached kernel physical address space
(kseg0)
Unmapped, 0.5GB
0x80000000
User virtual address space
(kuseg)
Mapped, 2.0GB
3.14 Joint TLB
For fast virtual-to-physical address translation, the RM5231A uses a large, fully associative TLB
that maps 96 virtual pages to their corresponding physical addresses. As indicated by its name, the
joint TLB (JTLB) is used for both instruction and data translations. The JTLB is organized as 48
pairs of even-odd entries, and maps a virtual address and address space identifier into the large, 64
GB physical address space.
Two mechanisms are provided to assist in controlling the amount of mapped space and the
replacement characteristics of various memory regions. First, the page size can be configured, on a
per-entry basis, to use page sizes in the range of 4 KB to 16 MB (in multiples of 4). The CP0 Page
Mask register is loaded with the desired page size of a mapping, and that size is stored into the
TLB along with the virtual address when a new entry is written. Thus, operating systems can
create special purpose maps; for example, an entire frame buffer can be memory mapped using
only one TLB entry.
The second mechanism controls the replacement algorithm when a TLB miss occurs. The
RM5231A provides a random replacement algorithm to select a TLB entry to be written with a
new mapping. However, the processor also provides a mechanism whereby a system specific
number of mappings can be locked into the TLB, thereby avoiding random replacement. This
mechanism uses the Wired register to ‘lock’ certain TLB entries and allows the operating system
0xFFFFFFFF
0xDFFFFFFF
0xBFFFFFFF
0x9FFFFFFF
0x7FFFFFFF
0x00000000
相關PDF資料 |
PDF描述 |
|---|---|
| RM5231A-300-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-300-HI | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-350-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5261A | RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary |
| RM5261A-250-H | RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary |
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