![](http://datasheet.mmic.net.cn/100000/IF180C52TXXX-20R_datasheet_3493957/IF180C52TXXX-20R_830.png)
830
32099I–01/2012
AT32UC3L016/32/64
Fix/Workaround
Use TWI0.TWCK on other pins.
10. TWIM Version Register reads zero
TWIM Version Register (VR) reads zero instead of 0x101
Fix/Workaround
None.
11. TWIS Version Register reads zero
TWIS Version Register (VR) reads zero instead of 0x112
Fix/Workaround
None.
12. SMBALERT bit may be set after reset
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after
system reset.
Fix/Workaround
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.
13. Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
14. TWIS stretch on Address match error
When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for
the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD
at the same time. This can cause a TWI timing violation.
Fix/Workaround
None.
35.4.15
PWMA
1.
PARAMETER register reads 0x2424
The PARAMETER register reads 0x2424 instead of 0x24.
Fix/Workaround
None.
2.
Writing to the duty cycle registers when the timebase counter overflows can give an
undefined result
The duty cycle registers will be corrupted if written when the timebase counter overflows. If
the duty cycle registers are written exactly when the timebase counter overflows at TOP, the
duty cycle registers may become corrupted.
Fix/Workaround
Write to the duty cycle registers only directly after the Timebase Overflow bit in the status
register is set.
3.
Open Drain mode does not work
The open drain mode does not work.
Fix/Workaround
None.