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型號(hào)：	R80C52EXXX-16D
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù)：	267/849頁(yè)
文件大?。?/td>	12530K
代理商：	R80C52EXXX-16D

32099I–01/2012

AT32UC3L016/32/64

ten to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g.

IFR), not all access methods are permitted.

Note that for ports with less than 32 bits, the corresponding control registers will have unused

bits. This is also the case for features that are not implemented for a specific pin. Writing to an

unused bit will have no effect. Reading unused bits will always return 0.

Configuration Protection

In order to protect the configuration of individual GPIO pins from software failure, configuration

bits for individual GPIO pins may be locked by writing a one to the corresponding bit in the LOCK

using the Peripheral Bus (PB) will not have an effect. The CPU Local Bus is not checked and

thus allowed to write to all bits in a CPU Local Bus mapped register no mather the LOCK value.

The registers required to clear bits in the LOCK register are protected by the access protection

mechanism described in Section 18.7.3, ensuring the LOCK mechanism itself is robust against

software failure.

Access Protection

In order to protect critical registers from software failure, some registers are protected by a key

protection mechanism. These registers can only be changed by first writing the UNLOCK regis-

ter, then the protected register. Protected registers are indicated in Table 18-2. The UNLOCK

sponding to the offset of the register to be modified.

The next write operation resets the UNLOCK register, so if the register is to be modified again,

the UNLOCK register must be written again.

Attempting to write to a protected register without first writing the UNLOCK register results in the

write operation being discarded, and the Access Error bit in the Access Status Register

(ASR.AE) will be set.

Table 18-2.

GPIO Register Memory Map

Register

Function

Register Name

Protection

Protection

GPIO Enable Register

GPIO Enable Register

GPIO Enable Register

GPIO Enable Register

Peripheral Mux Register 0

Peripheral Mux Register 0

Peripheral Mux Register 0

Peripheral Mux Register 0

Peripheral Mux Register 1

Peripheral Mux Register 1

Peripheral Mux Register 1

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