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型號：	R80C52EXXX-16D
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù)：	801/849頁
文件大?。?/td>	12530K
代理商：	R80C52EXXX-16D

32099I–01/2012

AT32UC3L016/32/64

Figure 8-3.

Mapping from Page Buffer to Flash

Internally, the flash memory stores data in 64-bit doublewords. Therefore, the native data size of

the Page Buffer is also a 64-bit doubleword. All locations shown in Figure 8-3 are therefore dou-

bleword locations. Since the HSB bus only has a 32-bit data width, two 32-bit HSB transfers

must be performed to write a 64-bit doubleword into the Page Buffer. The FLASHCDW has logic

to combine two 32-bit HSB transfers into a 64-bit data before writing this 64-bit data into the

Page Buffer. This logic requires the word with the low address to be written to the HSB bus

before the word with the high address. To exemplify, to write a 64-bit value to doubleword X0

residing in page X, first write a 32-bit word to the byte address pointing to address X0, thereafter

write a word to the byte address pointing to address (X0+4).

The page buffer is word-addressable and should only be written with aligned word transfers,

never with byte or halfword transfers. The page buffer can not be read.

The page buffer is also used for writes to the User page.

Page buffer write operations are performed with 4 wait states. Any accesses attempted to the

FLASHCDW on the HSB bus during these cycles will be automatically stalled.

Writing to the page buffer can only change page buffer bits from one to zero, i.e. writing

0xAAAAAAAA to a page buffer location that has the value 0x00000000 will not change the page

buffer value. The only way to change a bit from zero to one is to erase the entire page buffer with

the Clear Page Buffer command.

All locations are doubleword locations

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