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型號(hào)：	R80C52EXXX-16D
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù)：	584/849頁(yè)
文件大?。?/td>	12530K
代理商：	R80C52EXXX-16D

32099I–01/2012

AT32UC3L016/32/64

The signal names corresponds to the groups A and B of analog comparators. For normal mode,

the mapping from input signal names in the block diagram to the signal names is given in Table

Product Dependencies

In order to use this module, other parts of the system must be configured correctly, as described

I/O Lines

The ACIFB pins are multiplexed with other peripherals. The user must first program the I/O Con-

troller to give control of the pins to the ACIFB.

Power Management

If the CPU enters a sleep mode that disables clocks used by the ACIFB, the ACIFB will stop

functioning and resume operation after the system wakes up from sleep mode.

The clock for the ACIFB bus interface (CLK_ACIFB) is generated by the Power Manager. This

clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-

able the ACIFB before disabling the clock, to avoid freezing the ACIFB in an undefined state.

The ACIFB uses a GCLK as clock source for the Analog Comparators. The user must set up this

GCLK at the right frequency. The CLK_ACIFB clock of the interface must be at least 4x the

GCLK frequency used in the comparators. The GCLK is used both for measuring the startup

time of a comparator, and to give a frequency for the comparisons done in Continuous Measure-

Refer to the Electrical Characteristics chapter for GCLK frequency limitations.

Positive reference pin for Analog Comparator B n

Negative reference pin for Analog Comparator B n

Reference Voltage for all comparators selectable for INN

Table 27-3.

Signal Name Mapping

Pin Name

Channel Number

Normal Mode

Table 27-2.

I/O Line Description

Pin Name

Pin Description

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