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您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67717 > R80C52EXXX-16D (TEMIC SEMICONDUCTORS) 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 PDF資料下載

型號(hào)：	R80C52EXXX-16D
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù)：	802/849頁(yè)
文件大?。?/td>	12530K
代理商：	R80C52EXXX-16D

32099I–01/2012

AT32UC3L016/32/64

The aWire debug interface is reset after leaving Shutdown mode

If the aWire debug mode is used as debug interface and the program enters Shutdown

mode, the aWire interface will be reset when the part receives a wakeup either from the

WAKE_N pin or the AST.

Fix/Workaround

In 3.3V Single Supply Mode, the Analog Comparator inputs affects the device’s ability

to start

When using the 3.3V Single Supply Mode the state of the Analog Comparator input pins can

affect the device’s ability to release POR reset. This is due to an interaction between the

Analog Comparator input pins and the POR circuitry. The issue is not present in the 1.8 V

Supply Mode or the 3.3V Supply Mode with 1.8V Regulated I/O Lines.

Fix/Workaround

ACREFN (pin PA16) must be connected to GND until the POR reset is released and the

Analog Comparator inputs should not be driven higher than 1.0 V until the POR reset is

Increased Power Consumption in VDDIO in sleep modes

If OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis-

abled, this will lead to an increased power consumption in VDDIO.

Fix/Workaround

Solution 1: Disable OSC0 by writing a zero to the Oscillator Enable bit in the System Control

Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before going to a

sleep mode where OSC0 is disabled.

Solution 2: Pull down or up XIN0 or XOUT0 with 1MOhm resistor.

I/O Pins

PA17 has low ESD tolerance

PA17 only tolerates 500V ESD pulses (Human Body Model).

Fix/Workaround

Care must be taken during manufacturing and PCB design.

Not sampled.

Processor and Architecture

RETS behaves incorrectly when MPU is enabled

RETS behaves incorrectly when MPU is enabled and MPU is configured so that system

stack is not readable in unprivileged mode.

Fix/Workaround

Make system stack readable in unprivileged mode, or return from supervisor mode using

rete instead of rets. This requires:

1. Changing the mode bits from 001 to 110 before issuing the instruction. Updating the

mode bits to the desired value must be done using a single mtsr instruction so it is done

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