參數(shù)資料
型號(hào)： R5F61664RN50FPV
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-144
文件頁數(shù)： 9/70頁
文件大?。?/td> 8775K
代理商： R5F61664RN50FPV
Rev. 1.00 Feb. 18, 2008 Page xvii of xxxii
10.4
Transfer Modes ................................................................................................................. 466
10.4.1
Ordinary Modes ................................................................................................ 466
10.4.2
Cluster Transfer Modes..................................................................................... 467
10.5
Mode Operation ................................................................................................................ 468
10.5.1
Address Modes ................................................................................................. 468
10.5.2
Transfer Modes ................................................................................................. 471
10.5.3
Activation Sources ............................................................................................ 476
10.5.4
Bus Mode.......................................................................................................... 477
10.5.5
Extended Repeat Area Function ....................................................................... 478
10.5.6
Address Update Function Using Offset ............................................................ 481
10.5.7
Registers during EXDMA Transfer Operation ................................................. 485
10.5.8
Channel Priority Order...................................................................................... 490
10.5.9
Basic Bus Cycles .............................................................................................. 491
10.5.10
Bus Cycles in Dual Address Mode ................................................................... 492
10.5.11
Bus Cycles in Single Address Mode................................................................. 501
10.5.12
Operation Timing in Each Mode ...................................................................... 506
10.6
Operation in Cluster Transfer Mode ................................................................................. 517
10.6.1
Address Mode ................................................................................................... 517
10.6.2
Setting of Address Update Mode ...................................................................... 522
10.6.3
Caution for Combining with Extended Repeat Area Function ......................... 523
10.6.4
Bus Cycles in Cluster Transfer Dual Address Mode ........................................ 523
10.6.5
Operation Timing in Cluster Transfer Mode .................................................... 526
10.7
Ending EXDMA Transfer................................................................................................. 534
10.8
Relationship among EXDMAC and Other Bus Masters................................................... 537
10.8.1
CPU Priority Control Function Over EXDMAC .............................................. 537
10.8.2
Bus Arbitration with Another Bus Master ........................................................ 538
10.9
Interrupt Sources...............................................................................................................539
10.10 Usage Notes ...................................................................................................................... 542
Section 11 Data Transfer Controller (DTC) ......................................................545
11.1
Features............................................................................................................................. 545
11.2
Register Descriptions ........................................................................................................ 547
11.2.1
DTC Mode Register A (MRA) ......................................................................... 548
11.2.2
DTC Mode Register B (MRB).......................................................................... 549
11.2.3
DTC Source Address Register (SAR)............................................................... 550
11.2.4
DTC Destination Address Register (DAR)....................................................... 551
11.2.5
DTC Transfer Count Register A (CRA) ........................................................... 551
11.2.6
DTC Transfer Count Register B (CRB)............................................................ 552
11.2.7
DTC enable registers A to F (DTCERA to DTCERF)...................................... 552
11.2.8
DTC Control Register (DTCCR) ...................................................................... 553
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