參數(shù)資料
型號: R5F61664RN50FPV
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-144
文件頁數(shù): 50/70頁
文件大?。?/td> 8775K
代理商: R5F61664RN50FPV
Section 1 Overview
Rev. 1.00 Feb. 18, 2008 Page 22 of 1416
REJ09B0412-0100
Classification
Pin Name
I/O
Description
Address bus
A23 to A0
Output
Output pins for the address bits.
Data bus
D15 to D0
Input/
output
Input and output for the bidirectional data bus. These pins
also output addresses when accessing an address–data
multiplexed I/O interface space.
BREQ
Input
External bus-master modules assert this signal to request
the bus.
BREQO
Output
Internal bus-master modules assert this signal to request
access to the external space via the bus in the external bus
released state.
BACK
Output
Bus acknowledge signal, which indicates that the bus has
been released.
BS-A/BS-B
Output
Indicates the start of a bus cycle.
AS
Output
Strobe signal which indicates that the output address on the
address bus is valid in access to the basic bus interface or
byte control SRAM interface space.
AH
Output
This signal is used to hold the address when accessing the
address-data multiplexed I/O interface space.
RD
Output
Strobe signal which indicates that reading from the basic bus
interface space is in progress.
RD/
WR-A/RD/WR-B Output
Indicates the direction (input or output) of the data bus.
LHWR
Output
Strobe signal which indicates that the higher-order byte (D15
to D8) is valid in access to the basic bus interface space.
LLWR
Output
Strobe signal which indicates that the lower-order byte (D7 to
D0) is valid in access to the basic bus interface space.
LUB
Output
Strobe signal which indicates that the higher-order byte (D15
to D8) is valid in access to the byte control SRAM interface
space.
Bus control
LLB
Output
Strobe signal which indicates that the lower-order byte (D7 to
D0) is valid in access to the byte control SRAM interface
space.
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