參數(shù)資料
型號: R5F61664RN50FPV
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-144
文件頁數(shù): 8/70頁
文件大小: 8775K
代理商: R5F61664RN50FPV
Rev. 1.00 Feb. 18, 2008 Page xvi of xxxii
9.3.1
DMA Source Address Register (DSAR) .......................................................... 366
9.3.2
DMA Destination Address Register (DDAR) .................................................. 367
9.3.3
DMA Offset Register (DOFR).......................................................................... 368
9.3.4
DMA Transfer Count Register (DTCR) ........................................................... 369
9.3.5
DMA Block Size Register (DBSR) .................................................................. 370
9.3.6
DMA Mode Control Register (DMDR)............................................................ 371
9.3.7
DMA Address Control Register (DACR) ......................................................... 380
9.3.8
DMA Module Request Select Register (DMRSR) ........................................... 386
9.4
Transfer Modes................................................................................................................. 387
9.5
Operations......................................................................................................................... 388
9.5.1
Address Modes ................................................................................................. 388
9.5.2
Transfer Modes ................................................................................................. 392
9.5.3
Activation Sources............................................................................................ 397
9.5.4
Bus Access Modes ............................................................................................ 399
9.5.5
Extended Repeat Area Function ....................................................................... 401
9.5.6
Address Update Function using Offset ............................................................. 404
9.5.7
Register during DMA Transfer ......................................................................... 408
9.5.8
Priority of Channels .......................................................................................... 413
9.5.9
DMA Basic Bus Cycle...................................................................................... 415
9.5.10
Bus Cycles in Dual Address Mode ................................................................... 416
9.5.11
Bus Cycles in Single Address Mode................................................................. 425
9.6
DMA Transfer End ........................................................................................................... 430
9.7
Relationship among DMAC and Other Bus Masters ........................................................ 433
9.7.1
CPU Priority Control Function Over DMAC ................................................... 433
9.7.2
Bus Arbitration among DMAC and Other Bus Masters ................................... 434
9.8
Interrupt Sources...............................................................................................................435
9.9
Usage Notes ...................................................................................................................... 438
Section 10 EXDMA Controller (EXDMAC) .................................................... 439
10.1
Features............................................................................................................................. 439
10.2
Input/Output Pins.............................................................................................................. 442
10.3
Registers Descriptions ...................................................................................................... 443
10.3.1
EXDMA Source Address Register (EDSAR)................................................... 445
10.3.2
EXDMA Destination Address Register (EDDAR)........................................... 446
10.3.3
EXDMA Offset Register (EDOFR).................................................................. 447
10.3.4
EXDMA Transfer Count Register (EDTCR).................................................... 448
10.3.5
EXDMA Block Size Register (EDBSR)........................................................... 449
10.3.6
EXDMA Mode Control Register (EDMDR) .................................................... 450
10.3.7
EXDMA Address Control Register (EDACR) ................................................. 459
10.3.8
Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7).................................... 465
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