參數(shù)資料
型號(hào): QT0086202TME
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 54/62頁
文件大?。?/td> 268K
代理商: QT0086202TME
82C814
Page 44
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
6.3
AC Characteristics
Sym
Parameter
Min
Max
Unit
Figure
Primary PCI Bus
t100
C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#,
PAR, SERR#, PERR# setup time to PCICLK rising
7
ns
6-1
t101
C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#,
PAR, SERR#, PERR# hold time from PCICLK rising
0
ns
6-2
t102
C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#,
PAR, SERR#, PERR# valid delay from PCICLK rising
2
11
ns
6-3
t103
REQ# setup time to PCICLK rising
12
ns
6-1
t104
REQ# hold time from PCICLK rising
0
ns
6-2
t105
GNT# valid delay from PCICLK rising
2
12
ns
6-3
Secondary PCI Bus
t200
CC/BE[3:0]#, CAD[31:0], CFRAME#, CIRDY#, CTRDY#, CSTOP#, CDEVSEL#,
CBLOCK#, CPAR, CSERR#, CPERR# setup time to PCICLK rising
7
ns
6-1
t201
CC/BE[3:0]#, CAD[31:0], CFRAME#, CIRDY#, CTRDY#, CSTOP#, CDEVSEL#,
CBLOCK#, CPAR, CSERR#, CPERR# hold time from PCICLK rising
0
ns
6-2
t202
CC/BE[3:0]#, CAD[31:0], CFRAME#, CIRDY#, CTRDY#, CSTOP#, CDEVSEL#,
CBLOCK#, CPAR, CSERR#, CPERR# valid delay from PCICLK rising
2
11
ns
6-3
t203
CREQ[3:0]# setup time to PCICLK rising
12
ns
6-1
t204
CREQ[3:0]# hold time from PCICLK rising
0
ns
6-2
t205
CGNT[3:0]# valid delay from PCICLK rising
2
12
ns
6-3
t206
PCIRQ[3:0]# setup time to PCICLK rising
5
ns
6-1
t207
PCIRQ[3:0]# hold time from PCICLK rising
3
ns
6-2
t208
PCIRQ[3:0]# valid delay from PCICLK rising
2
16
ns
6-3
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