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參數(shù)資料
| 型號： | QT0086202TME |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 43/62頁 |
| 文件大?。?/td> | 268K |
| 代理商： | QT0086202TME |
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82C814
912-3000-047
Revision: 1.0
Page 33
January 08, 1998
OPTi
PCICFG 54h
IRQ Driveback Protocol Address Bits:
-
When the 82C814 logic must generate an interrupt from any source, it follows the IRQ Driveback Protocol and toggles the REQ# line to
the host. Once it has the bus, it writes the changed IRQ information to the 32-bit I/O address specified in this register. The host interrupt
controller claims this cycle and latches the new IRQ values.
-
Bits 2:0 are reserved to be 000 and are read-only.
-
This register defaults to a value of 33333330h.
IRQ Driveback Address Register - Byte 0: Address Bits [7:0]
Default = 30h
PCICFG 55h
IRQ Driveback Address Register - Byte 1: Address Bits [15:8]
Default = 33h
PCICFG 56h
IRQ Driveback Address Register - Byte 2: Address Bits [23:16]
Default = 33h
PCICFG 57h
IRQ Driveback Address Register - Byte 3: Address Bits [31:24]
Default = 33h
PCICFG 58h
DRQ Remap Base Address Bits:
-
The distributed DMA protocol requires DMA controller registers for each DMA channel to be individually mapped into I/O space outside
the range claimed by ISA devices. Bits A[31:0] of this register specify that base; bits 7:0 are reserved (write 0) because the base
address can fall only on 256 byte boundaries.
-
The 82C814 logic uses this base address to forward accesses across the bridge to remote devices specified in the DMA Channel Selec-
tor Register.
DRQ Remap Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
PCICFG 59h
DRQ Remap Base Address Register - Byte 1: Address Bits [15:8]
Default = 00h
PCICFG 5Ah
DRQ Remap Base Address Register - Byte 2: Address Bits [23:16]
Default = 00h
PCICFG 5Bh
DRQ Remap Base Address Register - Byte 3: Address Bits [31:24]
Default = 00h
PCICFG 5Ch
DMA Channel Selector Register
Default = 00h
Channel 7
(DMAC2):
0 = Not claimed
1 = On slot
interface
Channel 6
(DMAC2):
0 = Not claimed
1 = On slot
interface
Channel 5
(DMAC2):
0 = Not claimed
1 = On slot
interface
DMAC respon-
sibility (RO):
0 = Secondary
(always)
1 = Master
Channel 3
(DMAC1):
0 = Not claimed
1 = On slot
interface
Channel 2
(DMAC1):
0 = Not claimed
1 = On slot
interface
Channel 1
(DMAC1):
0 = Not claimed
1 = On slot
interface
Channel 0
(DMAC1):
0 = Not claimed
1 = On slot
interface
PCICFG 5Dh
SMI Status Register (Write 1 to clear bit)
Default = 00h
Toggling of
PCICFG 3Eh[6]
Generated SMI
0 = No
1 = Yes
Dock/Undock
Event Gener-
ated SMI
0 = No
1 = Yes
Read of Card-
Bus Registers
(MEMOFST
0=FFFh) Gen-
erated SMI
0 = No
1 = Yes
Write of Card-
Bus Registers
(MEMOFST
0=FFFh) Gen-
erated SMI
0 = No
1 = Yes
Docking Win-
dow 3
generated SMI:
0 = No
1 = Yes
Docking Win-
dow 2
generated SMI:
0 = No
1 = Yes
Docking Win-
dow 1
generated SMI:
0 = No
1 = Yes
Docking Win-
dow 0
generated SMI:
0 = No
1 = Yes
Table 5-2
Specific Register Group - PCICFG 50h-5Fh (cont.)
7
6
5
4
3
2
1
0
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