
82C814
Page 24
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
PCICFG 08h
Revision Register (RO) Revision 1.0
Default = 10h
PCICFG 09h
Programming Interface Class Code Register (RO)
Default = 00h
PCICFG 0Ah
Class Code Register (RO) - Byte 0
Subclass Code bits: = 07h (PCI-to-Cardbus Bridge)
Default = 07h
PCICFG 0Bh
Class Code Register (RO) - Byte 1
Base Class Code bits: = 06h (Bus Bridge)
Default = 06h
PCICFG 0Ch
Cache Line Size Register
Not implemented
Default = 00h
PCICFG 0Dh
Latency Timer Register
Default = 00h
Indicates the time-out value for the primary PCI interface.
PCICFG 0Eh
Header Type Register
Default = 02h
Multi-function 
device (RO):
0 = No (always)
Layout type for 10-3Fh bytes bits [6:0] = 02h (PCI-to-CardBus Header Layout)
PCICFG 0Fh
BIST Register
Not implemented
Default = 00h
PCICFG 10h
CardBus Socket Status and Control Base Address Bits:
-
The 32-bit Cardbus Base Address Register selects the starting address in memory space of the CardBus socket status and 
control registers. 
-
Actual register addresses are calculated by adding the MEMOFST of the register to this base address. 
-
Bits [11:0] are read-only and are always 0, to indicate that the registers occupy 4KB of non prefetchable system memory space and 
starts on a 4KB boundary.
CardBus Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
PCICFG 11h
CardBus Base Address Register - Byte 1: Address Bits [15:8]
Default = 00h
PCICFG 12h
CardBus Base Address Register - Byte 2: Address Bits [23:16]
Default = 00h
PCICFG 13h
CardBus Base Address Register - Byte 3: Address Bits [31:24]
Default = 00h
PCICFG 14h
Capabilities Pointer (RO)
Default = F0h
Indicates the offset in the PCICFG space for the location of the first item in the Capabilities Linked List. This location is PCICFG F0h. 
PCICFG 15h
Reserved
Default = 00h
Table 5-1
Base Register Group - PCICFG 00h-4Fh (cont.)
7
6
5
4
3
2
1
0