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| 型號(hào)： | QT0086202TME |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 31/62頁 |
| 文件大小： | 268K |
| 代理商： | QT0086202TME |
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82C814
912-3000-047
Revision: 1.0
Page 21
January 08, 1998
OPTi
4.9.3
The 82C814 chip supports the Compaq standard of Serial
IRQs. This one wire approach is very compact compared to
the Intel two-wire approach, but if two devices on the line
want to share the same interrupt, there may be brief conten-
tion since both devices drive the line low on one clock and
Compaq Serial IRQ Implementation
high on the clock that immediately follows. Because of this
contention, OPTi cannot guarantee against chip hardware
failure if interrupts are shared in this mode.
The Compaq Serial IRQ scheme requires the register bits.
shown in Table 4-7.
QUIET
- PCICFG 4Eh[6] requests the next Serial IRQ cycle
to be Continuous or Quiet mode. In mobile applications, use
Continuous mode only. This is to guarantee that the host
gains control of the Serial IRQ for suspend and APM stop
clock. In application where the PCI clock never stops, use
either mode. PCICFG 4Fh[6] can be read to determine the
current state of the logic.
HALT
- PCICFG 4Eh[7] requests a temporary halt of the
Serial IRQ controller as soon as the current cycle has
returned to Idle state. Once in Halt state, the Serial IRQ con-
figuration can be changed. After the logic has been put in
Halt state, upon clearing this bit the logic will return to Contin-
uous mode. PCICFG 4Fh[7] can be read to determine the
current state of the logic.
4.9.3.1
The Compaq Serial IRQ protocol requires one additional PCI
sustained Tri-State pin, the IRQSER signal. For detailed
Serial IRQ operation, refer to the “Serialized IRQ for PCI Sys-
tems” specification.
Operation
After setting PCICFG 4Eh[0] = 1 to enable Compaq Serial
IRQ (CSIRQ) mode, the CSIRQ controller initiates a Continu-
ous mode Start frame. During the Data frame, the CSIRQ
logic samples the IRQSER input for the corresponding SMI,
IOCHCK#, and IRQ values, and then passes the sampled
values to the primary.
At the end of the Data frame, the CSIRQ controller will sam-
ple the QUIET and HALT bits to determine whether the next
Compaq Serial IRQ cycle will be Continuous mode, Quiet
mode, or a temporary Halt state.
If the next cycle is sampled to be Continuous mode,
IRQSER is asserted for three PCI clocks. Once the logic
enters Idle state, it checks whether the PMU stop PCI
clock request is pending. If so, the CSIRQ logic will stay in
the Idle state until the PMU request is removed.
If the next cycle is sampled to be Quiet mode, IRQSER is
asserted for two PCI clocks. Once the logic enters Idle
state, it samples the IRQSER input to begin the Quiet
mode cycle. Since the 82C814 has no control of the Start
frame, this mode is not recommended for mobile applica-
tion.
If the HALT bit is sampled active, then the CSIRQ logic
asserts IRQSER for three PCI clocks to tell all the Serial
IRQ devices that next cycle will be Continuous mode; the
logic then enters Halt state. In Halt state, CSIRQ configu-
ration can be changed. Clearing the HALT bit will immedi-
ately cause a Continuous mode Start frame to be
generated.
Once enabled, the Compaq Serial IRQ logic operates all the
time when docked; no clock stop synchronization is needed.
Table 4-7
Compaq SIRQ Control Bits
7
6
5
4
3
2
1
0
PCICFG 4Eh
Serial IRQ Control Register 1
Default = 00h
Compaq SIRQ
HALT mode
request:
0 = Active
1 = Halt
Compaq SIRQ
QUIET mode
request:
0 = Continuous
1 = Quiet
Compaq SIRQ
data frame
slots. Change
only when the
Serial IRQ logic
is disabled or in
Halt state.
0 = 17 slots
1 = 21 slots
Compaq SIRQ Start frame width
in PCI clocks. Change this setting
only when Serial IRQ is disabled
or in Halt state.
00 = 4 PCI clocks
01 = 6 PCI clocks
10 = 8 PCI clocks
11 = Reserved
Compaq SIRQ
(Compaq Serial
IRQ scheme):
0 = Disable
1 = Enable
PCICFG 4Fh
Serial IRQ Control Register 2
Default = 00h
Compaq SIRQ
in HALT state
(RO)
0 = No
1 = Yes
Compaq SIRQ
in QUIET state
(RO)
0 = No
1 = Yes
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