
82C814
Page 18
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
 Establish IRQ Driveback Address.
 Write PCICFG 54-
57h with an I/O address to use for IRQ driveback. The 
default value is 33333330h, but any unused value is fine. 
Ideally the address should be greater than FFFFh to pre-
vent conflicts with ISA I/O address space.
Write the same value to the IRQ Driveback registers in the 
host chipset (Viper-N+ or FireStar). The registers are at 
the same PCI offset, but different PCI device: PCIDV1 54-
57h.
 Select PCI Bus Number of Docking Station.
 PCICFG 
19h selects the PCI bus number on the secondary side of 
the bridge. A value of 01h is typical.
 Select Total Number of Downstream Buses.
 PCICFG 
1Ah selects the number of the last downstream PCI bus. A 
value of 01h is typical.
 Program the Time-out Value.
 PCICFG 1Bh should be set 
to FFh.
 Program the Latency Timer
. PCICFG 0Dh should be set 
to FFh.
 Select the Status Change Events.
 PCICFG 64h[3:0] 
select the events that will cause a status change interrupt 
in the future. Typically writing PCICFG 64h = 06h is ade-
quate. Also write PCICFG 60h = 0Fh to clear any pending 
events.
Table 4-5 summarizes the typical settings for system initial-
ization.
4.7.4
At idle, with no device attached, the CD1-2# pins are pulled
high internal to the 82C814 chip. CVS1-2 are driven low. All
other interface lines are pulled low at this time; the docking
interface itself can remain unpowered. The 82C814 monitors
the CD1-2 lines to determine a docking event.
Action Upon Attachment of Dock
When a docking station is attached, the 82C814 sees CD1#
and CD2# go low, because the docking station connector has
these lines hard-wired as follows:
 CD1# is connected to CVS1 for a 3.3V docking station, or 
to CVS2 for a 5.0V docking station.
 CD2# is connected to ground.
The 82C814 card detection sequencer waits for the time set
in PCICFG 50h[3], then performs a test on these lines to
determine the type of device attached. Once the test is com-
plete, the 82C814 generates an interrupt to the IRQ config-
ured in PCICFG 4Ch.
Table 4-5
Summary of Typical Settings (using IRQ5 for SMI) 
* These bits should be read first, then written to the same value.
Register
Byte 3
Byte 2
Byte 1
Byte 0
82C814 Register
PCICFG 4Ch
--
--
--
15h (IRQ5)
PCICFG 54h
33h
33h
33h
30h
PCICFG 0Ch
--
--
FFh
--
PCICFG 18h
FFh
01h
01h
00h
PCICFG 64h
--
--
--
06h
PCICFG 60h
--
--
--
0Fh
Viper N+ Register (assuming IRQ5)
PCIDV1 54h
33h
33h
33h
30h
SYSCFG 64h
--
--
--
****1***b(IRQ5)
SYSCFG 57h
--
--
--
01**0000b
SYSCFG 59h
--
--
--
**11****b
SYSCFG 1Eh
--
--
--
****1***b