參數(shù)資料
型號： QT0086202TME
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 36/62頁
文件大?。?/td> 268K
代理商： QT0086202TME
82C814
Page 26
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
PCICFG 20h
Memory Window 0 Limit Address Bits:
-
The 32-bit Memory Window 0 Limit Address Register selects the end address of Memory Window 0.
-
Bits [11:0] are read-only and are always 0.
-
The minimum window size is always 4KB.
Memory Window 0 Limit Address Register - Byte 0: Address Bits [7:0
Default = 00h
PCICFG 21h
Memory Window 0 Limit Address Register - Byte 1: Address Bits [15:8]
Default = 00h
PCICFG 22h
Memory Window 0 Limit Address Register - Byte 2: Address Bits [23:16]
Default = 00h
PCICFG 23h
Memory Window 0 Limit Address Register - Byte 3: Address Bits [31:24]
Default = 00h
PCICFG 24h
Memory Window 1 Base Address Bits:
-
The 32-bit Memory Window 1 Base Address Register selects the start address of one of two possible CardBus memory windows to the
slot interface.
-
Bits [11:0] are read-only and are always 0.
-
The memory windows are globally enabled by bit 04h[1] (Command Register).
-
Prefetching is enabled by bit 3Fh[1] (Bridge Control Register) and defaults to "enabled."
-
The Limit address can be set below the Base address to individually disable a window.
Memory Window 1 Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
PCICFG 25h
Memory Window 1 Base Address Register - Byte 1: Address Bits [15:8]
Default = F0h
PCICFG 26h
Memory Window 1 Base Address Register - Byte 2: Address Bits [23:16]
Default = FFh
PCICFG 27h
Memory Window 1 Base Address Register - Byte 3: Address Bits [31:24]
Default = FFh
PCICFG 28h
Memory Window 1 Limit Address Bits:
-
The 32-bit Memory Window 1 Limit Address Register selects the end address of Memory Window 1.
-
Bits [11:0] are read-only and are always 0.
-
The minimum window size is always 4KB.
Memory Window 1 Limit Address Register - Byte 0: Address Bits [7:0]
Default = 00h
PCICFG 29h
Memory Window 1 Limit Address Register - Byte 1: Address Bits [15:8]
Default = 00h
PCICFG 2Ah
Memory Window 1 Limit Address Register - Byte 2: Address Bits [23:16]
Default = 00h
PCICFG 2Bh
Memory Window 1 Limit Address Register - Byte 3: Address Bits [31:24]
Default = 00h
PCICFG 2Ch
I/O Window 0 Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
I/O Window 0 Base Address Bits:
-
The 32-bit I/O Window 0 Base Address Register selects the start address of one of two possible
CardBus I/O windows to the slot interface.
-
The I/O windows are globally enabled by bit 04h[0] (Command Register).
RO:
Always returns
0.
Decoding:
0 = 16-bit
(AD[31:16] = 0)
1 = 32-bit
PCICFG 2Dh
I/O Window 0 Base Address Register - Byte 1: Address Bits [15:8]
Default = F0h
PCICFG 2Eh
I/O Window 0 Base Address Register - Byte 2: Address Bits [23:16]
Default = FFh
PCICFG 2Fh
I/O Window 0 Base Address Register - Byte 3: Address Bits [31:24]
Default = FFh
Table 5-1
Base Register Group - PCICFG 00h-4Fh (cont.)
7
6
5
4
3
2
1
0
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