參數(shù)資料
型號(hào)： PPC440EPx-NpAfffTs
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 440EPx Embedded Processor
中文描述： 嵌入式處理器的PowerPC 440EPx
文件頁(yè)數(shù)： 89/94頁(yè)
文件大?。?/td> 738K
代理商： PPC440EPX-NPAFFFTS
Notes:
1. Clock speed is 166 MHz. T
SK
is referenced to MemClkOut falling edge. T
SA
and T
HA
are referenced to MemClkOut rising
edge.
2. The timing in this table assumes a single registered DIMM load on the outputs. To adjust the timing for unbuffered DIMMs,
use the following values by subtracting them from T
SA
and adding them to T
SK
and T
HA
:
5 loads adjust by 0.41 ns
9 loads adjust by 1.12 ns
18 loads adjust by 2.12 ns
3. To obtain adjusted T
SA
values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and subtract
T
SK
maximum (0.5T
CYC
T
SK
max).
4. To obtain adjusted T
HA
values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and add
T
SK
minimum (0.5T
CYC
+ T
SK
min).
Signal Name
T
SK
(ns)
T
SA
(ns)
Minimum
T
HA
(ns)
Minimum
Minimum
Maximum
MemAddr00:13
BA0:2
BankSel0:1
ClkEn
CAS
RAS
WE
-0.960
-0.270
3.27
2.04
440EPx – PPC440EPx Embedded Processor
Revision 1.26 – October 15, 2007
Preliminary Data Sheet
AMCC Proprietary
89
Table 25. I/O Timing—DDR SDRAM T
SK
, T
SA
, and T
HA
Table 26. I/O Timing—DDR SDRAM T
SD
and T
HD
Notes:
1. T
SD
and T
HD
are measured under worst case conditions.
2. Clock speed for the values in the table is 166 MHz.
3. The time values in the table include 1/4 of a cycle at 166 MHz (6 ns x 0.25 = 1.5 ns).
4. To obtain adjusted T
SD
and T
HD
values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4
of the cycle time for the lower clock frequency (for example, T
SD
1.5 + 0.25T
CYC
).
Signal Names
Reference Signal
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
T
SD
(ns)
1.37
1.41
1.40
1.41
1.45
1.40
1.46
1.45
1.46
T
HD
(ns)
1.23
1.18
1.17
1.20
1.18
1.18
1.17
1.10
1.18
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
MemData32:39, DM4
MemData40:47, DM5
MemData48:55, DM6
MemData56:63, DM7
ECC0:7, DM8
DDR SDRAM Read Operation
The read data capture logic is responsible for capturing the data outputs from the SDRAM devices and passing the
data back to the system clock domain. The data strobe signal (DQS) signals used to capture data are delayed to
ensure that the rising and falling edges of these strobes are in the middle of the valid window of data.
DDR devices send a DQS coincident with the read data so that the data can be reliably captured by the
PPC440EPx. The edges of these strobe signals are aligned with the data output by the SDRAM devices.
In order to reliably latch the data into a synchronizing FIFO, the PPC440EPx produces an internal, delayed version
of DQS. The amount of delay is user programmable. In the example shown in
Figure 12
, the delay is set to
approximately 25% of the system clock. A delay compensation circuit in the PPC440EPx keeps this delay
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