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參數(shù)資料
| 型號： | PPC440EPx-NpAfffTs |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440EPx Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440EPx |
| 文件頁數(shù)： | 67/94頁 |
| 文件大?。?/td> | 738K |
| 代理商： | PPC440EPX-NPAFFFTS |
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440EPx – PPC440EPx Embedded Processor
Revision 1.26 – October 15, 2007
Preliminary Data Sheet
AMCC Proprietary
67
Input Logic High 3.3V PCI
V
IH
0.5OV
DD
OV
DD
+0.5
V
1
Input Logic High 3.3V LVTTL
+2.0
+3.6
V
Input Logic High 2.5V CMOS, 3.3 V tolerant
+1.7
+3.6
V
Input Logic High 1.8V DDR2 (2.5V DDR1)
SV
REF
+
0.125 (0.15)
2.2 (3.0)
V
Input Logic Low 3.3V PCI
V
IL
0.5
0.35OV
DD
V
1
Input Logic Low 3.3V LVTTL
0
+0.8
V
Input Logic Low 2.5V CMOS
0
+0.7
V
Input Logic Low 1.8V DDR2 (2.5V DDR1)
-0.3 (-0.3)
SV
REF
0.125 (0.15)
V
Output Logic High 3.3V PCI
V
OH
0.9OV
DD
-
V
1
Output Logic High 3.3V LVTTL
+2.4
+3.6
V
Output Logic High 2.5V CMOS
+2.0
+2.7
V
Output Logic High 1.8V DDR2 (2.5V DDR1)
+0.95 (+1.7)
+1.95 (+2.7)
V
5
Output Logic Low 3.3V PCI
V
OL
-
0.1OV
DD
V
1
Output Logic Low 3.3V LVTTL
0
+0.4
V
Output Logic Low 2.5V CMOS
0
+0.4
V
Output Logic Low 1.8V DDR2 (2.5V DDR1)
0
+0.43 (+0.54)
V
5
Input Leakage Current (no pull-up or pull-down)
I
IL1
0
0
μ
A
Input Leakage Current for pull-down
I
IL2
0 (LPDL)
200 (MPUL)
μ
A
Input Leakage Current for pull-up
I
IL3
150 (LPDL)
0 (MPUL)
μ
A
Input Max Allowable Overshoot 3.3V LVTTL
V
IMAO
+3.9
V
Input Max Allowable Undershoot 3.3V LVTTL
V
IMAU
0.6
V
Output Max Allowable Overshoot 3.3V LVTTL
V
OMAO
+3.9
V
Output Max Allowable Undershoot 3.3V LVTTL
V
OMAU3
0.6
V
Case Temperature
T
C
40
+100
°
C
6
Notes:
1. PCI drivers meet PCI specifications.
2. SV
REF
= SOV
DD
/2. SOV
DD
= +1.8 V for DDR2 memory or +2.5 V for DDR1 memory.
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440EPx. See “Absolute Maximum Ratings” on page 66.
4. Startup sequencing of the power supply voltages is not required. A power-down cycle must complete (OVDD and VDD are below
+0.4 V) before a new power-up cycle is started
5. At I
OH
= I
OL
= 10 ma.
6. Case temperature, T
C
, is measured at top center of case surface with device soldered to a circuit board.
Table 10. Recommended DC Operating Conditions (Sheet 2 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440EPx-SpAfffTs | PowerPC 440EPx Embedded Processor |
| PPC440EP | Power PC 440EP Embedded Processor |
| PPC440EP-3pbfffCx | Power PC 440EP Embedded Processor |
| PPC440GP-3CC333C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400C | Power PC 440GP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EPX-NTA400E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-NTA400EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-NTA533E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-NTA533EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-NTA667E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
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