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參數(shù)資料
| 型號： | PPC440EPx-NpAfffTs |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440EPx Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440EPx |
| 文件頁數(shù)： | 12/94頁 |
| 文件大?。?/td> | 738K |
| 代理商： | PPC440EPX-NPAFFFTS |
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440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
12
AMCC Proprietary
Revision 1.26 – October 15, 2007
– Slave-terminated double word and quadword fixed length bursts
– Master-terminated variable length bursts
Guarded memory access on 4 KB boundaries
Data parity checking
Data transfers occur at PLB bus speeds.
Power management
Internal Buses
The PowerPC 440EPx features six standard internal buses: two Processor Local Buses (PLBs), three On-Chip
Peripheral Buses (OPBs), and the Device Control Register Bus (DCR). The high performance, high bandwidth
cores such as the PowerPC 440 processor, the DDR SDRAM memory controller, and the PCI bridge connect to
the PLBs. OPB0 hosts lower data rate peripherals. OPB1 is dedicated to USB 2.0 Device support, and OPB2 is
dedicated to USB 2.0 Host. The daisy-chained DCR provides a lower bandwidth path for passing status and
control information between the processor and the other on-chip cores.
Features include:
PLB4 (128-bit)
– 128-bit implementation of the PLB architecture
– Separate and simultaneous read and write data paths
– 36-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte-enable capability supporting unaligned transfers
– 32- and 64-byte burst transfers
– 166 MHz, maximum 5.3 GB/s (simultaneous read and write)
– Processor:bus clock ratios of N:1 and N:2
PLB3 (64-bit)
– 64-bit implementation of the PLB architecture
– 32-bit address
– 166 MHz (1:1 ratio with PLB4), maximum 1.3 GB/s (no simultaneous read and write)
OPBs (OPB0, OPB1, and OPB2)
– 32-bit data path
– 32-bit address
– 83 MHz
DCR
– 32-bit data path
– 10-bit address
Security Function (optional)
The built-in security function (PPC440EPx-S only) is a cryptographic engine attached to the 128-bit PLB with built-
in DMA and interrupt controllers.
Features include:
Federal Information Processing Standard (FIPS) 140-2 design
Support for an unlimited number of Security Associations (SA)
Different SA formats for each supported protocol (IPsec/SSL/TLS/sRTP)
Internet Protocol Security (IPSec) features
Full packet transforms (ESP & AH)
Complete header and trailer processing (IPv4 and IPv6)
Multi-mode automatic padding
"Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers
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| PPC440EPx-SpAfffTs | PowerPC 440EPx Embedded Processor |
| PPC440EP | Power PC 440EP Embedded Processor |
| PPC440EP-3pbfffCx | Power PC 440EP Embedded Processor |
| PPC440GP-3CC333C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400C | Power PC 440GP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EPX-NTA400E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-NTA400EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-NTA533E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-NTA533EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-NTA667E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
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