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參數(shù)資料
| 型號： | PPC440EPx-NpAfffTs |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440EPx Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440EPx |
| 文件頁數(shù)： | 55/94頁 |
| 文件大小： | 738K |
| 代理商： | PPC440EPX-NPAFFFTS |
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440EPx – PPC440EPx Embedded Processor
Revision 1.26 – October 15, 2007
Preliminary Data Sheet
AMCC Proprietary
55
Signal Descriptions
The PPC440EPx embedded controller is packaged in a 680-ball thermally enhanced plastic ball grid array
(TE-PBGA). The following tables describe the package level pin-out.
Group
No. of Pins
Total Signal Pins
367
AV
DD
1
AGND
1
EAV
DD
1
EAGND
1
UAV
DD
4
UAGND
5
OV
DD
26
SOV
DD
14
EOV
DD
12
V
DD
56
GND
192
Total Power Pins
313
Reserved
0
Total Pins
680
In the table
Table 8
on page 57, each I/O signal is listed along with a short description of its function. Active-low
signals (for example, RAS) are marked with an overline. Please see
Table 5
on page 21 for the pin (ball) number to
which each signal is assigned.
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases,
the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same
pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in
Table 5
on page 21. It is expected that in any single application a particular pin will always be programmed to serve the
same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise
be possible.
Note:
Signals multiplexed with GPIO default to GPIO receivers and float after reset. Initialization software must
configure the GPIO registers for the desired function as described in the GPIO chapter of the user’s manual. Any of
these signals requiring a particular state prior to running initialization code must be terminated with pull ups or pull
downs.
Multipurpose Signals
In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address
pins (PerAddr) are used as outputs by the PPC440EPx to broadcast an address to external slave devices when the
PPC440EPx has control of the external bus. When, during normal operation, an external master gains ownership
Table 7. Pin Summary
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440EPx-SpAfffTs | PowerPC 440EPx Embedded Processor |
| PPC440EP | Power PC 440EP Embedded Processor |
| PPC440EP-3pbfffCx | Power PC 440EP Embedded Processor |
| PPC440GP-3CC333C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400C | Power PC 440GP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EPX-NTA400E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-NTA400EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-NTA533E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-NTA533EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-NTA667E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
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