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參數(shù)資料
| 型號(hào)： | PPC440EPx-NpAfffTs |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440EPx Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440EPx |
| 文件頁數(shù)： | 16/94頁 |
| 文件大小： | 738K |
| 代理商： | PPC440EPX-NPAFFFTS |
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440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
16
AMCC Proprietary
Revision 1.26 – October 15, 2007
Serial Ports (UART)
Features include:
Up to four ports in the following combinations:
– One 8-pin (UART0)
– Two 4-pin (UART0 and UART1)
– One 4-pin (UART0) and two 2-pin (UART1 and UART2)
– Four 2-pin (UART0, UART1, UART2, and UART3)
Selectable internal or external serial clock to allow wide range of baud rates
Register compatibility with NS16750 register set
Complete status reporting capability
Fully programmable serial-interface characteristics
Supports DMA using internal DMA function on PLB3
IIC Bus Controller
Features include:
Two IIC interfaces provided
Support for Philips Semiconductors I
2
C Specification, dated 1995
Operation at 100 kHz or 400 kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Provides full management of all IIC bus protocols
Programmable error recovery
Includes an integrated bootstrap controller (BSC) that is multiplexed with the second IIC interface
Serial Peripheral Controller (SPI/SCP)
The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous,
character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on
the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.
Features include:
Three-wire serial port interface
Full-duplex synchronous operation
SCP bus master
OPB bus slave
Programmable clock rate divider
Clock inversion
Reverse data
Local data loop back for test
Universal Serial Bus 2.0 (USB)
The USB 2.0 interface provides both device and host support. One interface provides host or device support and
operates through an internal PHY. The other interface provides device support only through the UTMI interface
with no internal PHY.
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| PPC440EP | Power PC 440EP Embedded Processor |
| PPC440EP-3pbfffCx | Power PC 440EP Embedded Processor |
| PPC440GP-3CC333C | Power PC 440GP Embedded Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EPX-NTA400E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-NTA400EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-NTA533E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-NTA533EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-NTA667E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
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