參數(shù)資料
型號(hào): PPC440EPx-NpAfffTs
廠(chǎng)商: Applied Micro Circuits Corp.
英文描述: PowerPC 440EPx Embedded Processor
中文描述: 嵌入式處理器的PowerPC 440EPx
文件頁(yè)數(shù): 87/94頁(yè)
文件大小: 738K
代理商: PPC440EPX-NPAFFFTS
Signal Path
Output Current (mA)
I/O H (maximum)
I/O L (maximum)
Write Data
MemData00:63
ECC0:7
DM0:8
MemClkOut
MemAddr00:13
BA0:2
RAS
CAS
WE
BankSel0:1
ClkEn
DQS0:8
MemODT0:1
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
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10
10
440EPx – PPC440EPx Embedded Processor
Revision 1.26 – October 15, 2007
Preliminary Data Sheet
AMCC Proprietary
87
Table 22. DDR SDRAM Output Driver Specifications
DDR SDRAM Write Operation
The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes. The following data is
generated by means of simulation and includes logic, driver, package RLC, and lengths. Values are calculated
over best case and worst case processes with speed, junction temperature, and voltage as follows:
Case
Process Speed
Junction Temperature (°C)
Voltage (V)
Best
Fast
40
+1.6
Worst
Slow
+125
+1.425
Note:
In the following tables and timing diagrams, minimum values are measured under best case conditions and
maximum values are measured under worst case conditions. The timing numbers in the following sections are
obtained using a simulation that assumes a model as shown in
Figure 10
.
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Table 23. DDR SDRAM Write Operation Conditions
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