PowerPC 750CX RISC Microprocessor Datasheet
November 13, 2000
Version 1.1
Page 5
List of Tables
Table 1: Absolute Maximum Ratings ......................................................................................... 11
Table 2: Recommended Operating Conditions ........................................................................... 12
Table 3: Package Thermal Characteristics .................................................................................. 12
Table 4: DC Electrical Specifications ......................................................................................... 13
Table 5: Power Consumption ...................................................................................................... 14
Table 6: Clock AC Timing Specifications .................................................................................. 15
Table 7: 60X Bus Input Timing Specifications ........................................................................... 16
Table 8: 60X Bus Output AC Timing Specifications ................................................................. 17
Table 9: JTAG AC Timing Specifications (Independent of SYSCLK) ...................................... 20
Table 10:Signal Listing for the 256 PBGA Package ................................................................... 26
Table 11:Signals Missing from Previous PowerPC 750 Designs ................................................ 27
Table 12:Signal Locations ............................................................................................................ 28
Table 13:Voltage and Ground Assignments ................................................................................ 29
Table 14:PowerPC 750CX Microprocessor PLL Configuration ................................................. 30
Table 15:Driver Impedance Characteristics ................................................................................. 32
Table 16:Input-Output Usage ....................................................................................................... 34
Table 17:Summary of Design Migration ..................................................................................... 39
Table 18:Process Version Register (PVR) ................................................................................... 40
Table 19:Document History ......................................................................................................... 41