參數(shù)資料
型號: PowerPC 750CX
廠商: IBM Microeletronics
英文描述: 32-Bit Reduced Instruction Set Computer (RISC) Microprocessors(32位精簡指令集微處理器)
中文描述: 32位精簡指令集計算機(jī)(RISC)微處理器(32位精簡指令集微處理器)
文件頁數(shù): 20/44頁
文件大小: 562K
代理商: POWERPC 750CX
PowerPC 750CX RISC Microprocessor Datasheet
Page 20
Version 1.1
November 13, 2000
Figure 7 provides the JTAG clock input timing diagram.
Table 9: JTAG AC Timing Specifications (Independent of SYSCLK)
See Table 2 on page 12 for operating conditions..
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
25
MHz
1
TCK cycle time
40
ns
2
TCK clock pulse width measured at 1.1V
15
ns
3
TCK rise and fall times
0
2
ns
4
4
Specification obsolete, intentionally omitted
5
TRST assert time
25
ns
1
6
Boundary-scan input data setup time
0
ns
2
7
Boundary-scan input data hold time
13
ns
2
8
TCK to output data valid
8
ns
3, 5
9
TCK to output high impedance
3
19
ns
3, 4
10
TMS, TDI data setup time
0
ns
11
TMS, TDI data hold time
15
ns
12
TCK to TDO data valid
2.5
12
ns
5
13
TCK to TDO high impedance
3
9
ns
4
14
TCK to output data invalid (output hold)
0
ns
Note:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum specification guaranteed by characterization and not tested.
Figure 7. JTAG Clock Input Timing Diagram
1
2
2
3
3
VM = Midpoint Voltage (0.9V)
VM
TCK
VM
VM
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