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參數(shù)資料
| 型號(hào)： | PowerPC 750CX |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Reduced Instruction Set Computer (RISC) Microprocessors(32位精簡指令集微處理器) |
| 中文描述： | 32位精簡指令集計(jì)算機(jī)（RISC）微處理器（32位精簡指令集微處理器） |
| 文件頁數(shù)： | 14/44頁 |
| 文件大小： | 562K |
| 代理商： | POWERPC 750CX |
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PowerPC 750CX RISC Microprocessor Datasheet
Page 14
Version 1.1
November 13, 2000
Table 5 provides the power consumption for the PowerPC 750CX.
5.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the PowerPC 750CX. After fabrication, parts are sorted by
maximum processor core frequency as shown in the Section 5.2.1 on Page 14, and tested for conformance to the AC
specifications for that frequency. The processor core frequency is determined by the bus (SYSCLK) frequency and the
settings of the PLL_CFG(0-3) signals.
5.2.1 Clock AC Specifications
Table 6 provides the clock AC timing specifications as defined in Figure 2.
Table 5: Power Consumption
See Table 2 on page 12 for recommended operating conditions.
Representative Processor Frequency
Unit
Notes
366MHz
400MHz
433MHz
466MHz
500MHz
Full-On Mode
Typical ( V
DD
= 1.8V) (OV
DD
=1.8)(65C)
3.3
3.5
3.7
4.0
4.3
W
1,3,4,5
Maximum ( V
DD
= 1.9V) (OV
DD
=1.9)(105C)
6.7
7.1
7.4
7.7
8.3
W
1,2,4,5
Typical ( V
DD
= 1.8V) (OV
DD
=2.5)(65C)
3.3
3.5
3.7
4.0
4.3
W
1,3,4,5
Maximum ( V
DD
= 1.9V) (OV
DD
=2.62)(105C)
6.7
7.1
7.4
7.7
8.3
W
1,2,4,5
Doze Mode
Maximum ( )
TBD
TBD
TBD
TBD
TBD
W
1,2,4,5
Nap Mode
Maximum ( )
TBD
TBD
TBD
TBD
TBD
W
1,2,4,5
Sleep Mode
TBD
TBD
TBD
TBD
TBD
W
1,2,4,5
Note:
1. These values apply for all valid 60X buses. The values do not include I/O Supply Power (OV
DD
) or PLL/DLL supply power (AV
DD
). OV
DD
power is system
dependent, but is typically <10% of V
DD
power.
2. Maximum power is measured at V
DD
= 1.90V and assumes worst case process parameters.
3. Typical power is an estimate of the average value measured at V
DD
= AV
DD
= 1.8V, OV
DD
= 1.80/2.5V in a system executing typical applications and
benchmark sequences.
4. Full-on mode uses a worst case instruction mix.
5. Guaranteed by design and characterization, and is not tested.
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