參數(shù)資料
型號: PowerPC 750CX
廠商: IBM Microeletronics
英文描述: 32-Bit Reduced Instruction Set Computer (RISC) Microprocessors(32位精簡指令集微處理器)
中文描述: 32位精簡指令集計(jì)算機(jī)(RISC)微處理器(32位精簡指令集微處理器)
文件頁數(shù): 15/44頁
文件大小: 562K
代理商: POWERPC 750CX
PowerPC 750CX RISC Microprocessor Datasheet
November 13, 2000
Version 1.1
Page 15
Figure 2. SYSCLK Input Timing Diagram
Table 6: Clock AC Timing Specifications
1,6
See Table 2 on page 12, for recommended operating conditions.
Num
Characteristic
Value
Unit
Notes
Min
Max
Processor frequency
300
500
MHz
6
SYSCLK frequency
31
133
MHz
1
1
SYSCLK cycle time
7.5
32
ns
2,3
SYSCLK rise and fall time (slew rate)
1.0
2.0
volt/ns
2,3
4
SYSCLK duty cycle measured at 0.8V
25
75
%
3
SYSCLK jitter
±
150
ps
4,3
Internal PLL relock time
100
μ
s
5
Note:
1. Caution: The SYSCLK frequency and the PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) fre-
quency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal
description in Section “PLL Configuration,” on page 28 for valid PLL_CFG[0-3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 to 1.2V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under
±
150ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock
after a stable V
and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time
during the power-on reset sequence.
6. For applications with processor frequencies below 300MHz, application conditions need to be investigated.
VM
CV
IL
CV
IH
1
2
4
3
4
SYSCLK
VM - Midpoint Voltage (0.8V)
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