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參數(shù)資料
| 型號： | PowerPC 750CX |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Reduced Instruction Set Computer (RISC) Microprocessors(32位精簡指令集微處理器) |
| 中文描述： | 32位精簡指令集計(jì)算機(jī)（RISC）微處理器（32位精簡指令集微處理器） |
| 文件頁數(shù)： | 39/44頁 |
| 文件大?。?/td> | 562K |
| 代理商： | POWERPC 750CX |
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PowerPC 750CX RISC Microprocessor Datasheet
November 13, 2000
Version 1.1
Page 39
7.9.4 DBWO/L2_TSTCLK
One pin has two functions: DBWO and L2_TSTCLK dependent upon the LSSD_MODE pin. When the LSSD_MODE
pin is low, the DBWO/L2_TSTCLK pin is set to L2_TSTCLK function which is used during the manufacturing process
for testing.
When the LSSD_MODE pin is pulled to the high state, the DBWO/L2_TSTCLK pin is set to DBWO which is identical
to those descriptions given in earlier versions of the PowerPC 750CX RISC Microprocessor’s User’s Manuals.
7.9.5 PowerPC 750CX Revision Level Migration
The following table summarizes the design changes for the respective PowerPC 750CX design revision lev-
els.
8.0 Ordering Information
This section provides the part numbering nomenclature for the PowerPC 750CX. Note that the individual part numbers
correspond to a maximum processor core frequency. For available frequencies, contact your local IBM sales office.
In addition to the processor frequency and bus ratio, the part numbering scheme also consists of a part modifier. The part
modifier allows for the availability of future enhanced parts (i.e., lower voltage, lower power, higher performance, etc.).
Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part
numbering scheme for identification purposes only.
Figure 19 provides the IBM part numbering nomenclature for the PowerPC 750CX.
Table 17: Summary of Design Migration
DD1.0
DD2.0
DD2.1
DD2.2
PVR
0x00080100
0x00080100
0x00082201
0x00082202
L1 Data Bus Width
64-Bits
256-Bits
256-Bits
256-Bits
DPM
Enabled
Disabled
Disabled
Disabled
Test Pin
CHKSTP_OUT removed
CLKOUT/
CHKSTP_OUT share
a pin
CLKOUT/
CHKSTP_OUT share a
pin
CLKOUT/
CHKSTP_OUT share a
pin
32-Bit Mode
Not available
Available
Available
Available
Floating Bus
Pull-ups required
No pull-ups
No pull-ups
No pull-ups
DBWO Pin
Absent
Absent
Present
Present
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