參數(shù)資料
型號: PowerPC 405GP
廠商: IBM Microeletronics
英文描述: 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器)
中文描述: 32位RISC嵌入式控制器(32位的RISC結(jié)構(gòu)嵌入式控制器)
文件頁數(shù): 8/58頁
文件大?。?/td> 878K
代理商: POWERPC 405GP
PowerPC 405GP Embedded Processor Data Sheet
8
On-Chip Memory
The On-Chip Memory feature comprises a memory controller and a one-port 4KB static RAM (SRAM)
accessed by the processor core.
Features include:
Low-latency access to critical instructions and data
Performance identical to cache hits without misses
Contents change only under program control
PLB to PCI Interface
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC
processor and local memory. This interface is compliant with version 2.2 of the PCI Specification.
Features include:
Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use
is optional and can be disabled for systems which employ an external arbiter.
PLB 3.0 Compliant
PLB bus frequency up to 133MHz
64-bit PLB Master
32-bit PLB Slave
PCI bus frequency up to 66MHz
- Synchronous operation at 1/n fractions of PLB speed (n = 1 to 4) to 33MHz maximum
- Asynchronous operation from 1/8 PLB frequency to 66MHz maximum
32-bit PCI Address/Data Bus
Power Management:
- PCI Bus Power Management v1.1 compliant
Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI
Buffering between PLB and PCI:
- PCI Target 64-byte write post buffer
- PCI Target 96-byte read prefetch buffer
- PLB Slave 8-byte write post buffer
- PLB Slave 64-byte read prefetch buffer
Error tracking/status
Supports PCI Target side configuration
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