參數(shù)資料
型號： PowerPC 405GP
廠商： IBM Microeletronics
英文描述： 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器)
中文描述： 32位RISC嵌入式控制器（32位的RISC結(jié)構(gòu)嵌入式控制器）
文件頁數(shù)： 37/58頁
文件大?。?/td> 878K
代理商： POWERPC 405GP
PowerPC 405GP Embedded Processor Data Sheet
37
BA1
BA0
Bank Address supporting up to 4 internal banks
O
3.3V LVTTL
RAS
Row Address Strobe
O
3.3V LVTTL
CAS
Column Address Strobe
O
3.3V LVTTL
DQM0
DQM1
DQM2
DQM3
DQM for byte lanes 0 (MemData0:7),
1 (MemData8:15),
2 (MemData16:23), and
3 (MemData24:31)
O
3.3V LVTTL
DQMCB
DQM for ECC check bits
O
3.3V LVTTL
ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
ECC6
ECC7
ECC check bits 0:7
I/O
3.3V LVTTL
4
BankSel0
BankSel1
BankSel2
BankSel3
Select up to four external SDRAM banks
O
3.3V LVTTL
WE
Write Enable
O
3.3V LVTTL
ClkEn0
ClkEn1
SDRAM Clock Enable
O
3.3V LVTTL
MemClkOut0
MemClkOut1
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a
PLL or zero-delay buffer.
O
3.3V LVTTL
Signal Functional Description
(Part 5 of 12)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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