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參數(shù)資料
| 型號： | PowerPC 405GP |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC結構嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC結構嵌入式控制器） |
| 文件頁數(shù)： | 41/58頁 |
| 文件大?。?/td> | 878K |
| 代理商： | POWERPC 405GP |
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PowerPC 405GP Embedded Processor Data Sheet
41
External MASTER Peripheral Interface
PerClk
Peripheral clock to be used by an external master and by
synchronous peripheral slaves
O
5V tolerant
3.3V LVTTL
ExtReset
Peripheral reset to be used by an external master and by
synchronous peripheral slaves
O
5V tolerant
3.3V LVTTL
HoldReq
Hold Request, used by an external master to request ownership
of the peripheral bus
I
5V tolerant
Rcvr
1, 5
HoldAck
Hold Acknowledge, used by the PPC405GP to transfer ownership
of peripheral bus to an external master
O
5V tolerant
3.3V LVTTL
6
ExtReq
ExtReq is used by an external master to indicate it is prepared to
transfer data
I
5V tolerant
Rcvr
1, 4
ExtAck
ExtAck is used by the PPC405GP to indicate that a data transfer
occurred.
O
5V tolerant
3.3V LVTTL
6
HoldPri
Used by an external master to indicate the priority of a given
transfer (0 = high, 1 = low)
I
5V tolerant
Rcvr
1, 4
BusReq
Used when the PPC405GP needs to regain control of peripheral
interface from an external Master
O
5V tolerant
3.3V LVTTL
PerErr
Used as an input. Used to record external Master errors and
external slave peripheral errors
I
5V tolerant
Rcvr
1, 5
Internal Peripheral Interface
UARTSerClk
Serial Clock used to provide an alternative clock to the internally
generated serial clock. Used in cases where the allowable
internally generated baud rates are not satisfactory. This input
can be individually connected to either UART.
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Rx
UART0 Serial Data In
I
5V tolerant
3.3V LVTTL
1, 4
UART0_Tx
UART0 Serial Data Out
O
5V tolerant
3.3V LVTTL
6
UART0_DCD
UART0 Data Carrier Detect
I
5V tolerant
3.3V LVTTL
1, 4
UART0_DSR
UART0 Data Set Ready
I
5V tolerant
3.3V LVTTL
1, 4
UART0_CTS
UART0 Clear To Send
I
5V tolerant
3.3V LVTTL
1, 4
UART0_DTR
UART0 Data Terminal Ready
O
5V tolerant
3.3V LVTTL
6
UART0_RTS
UART0 Request To Send
O
5V tolerant
3.3V LVTTL
6
UART0_RI
UART0 Ring Indicator
I
5V tolerant
3.3V LVTTL
Rcvr
1, 4
Signal Functional Description
(Part 9 of 12)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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