參數(shù)資料
型號(hào)： PowerPC 405GP
廠商： IBM Microeletronics
英文描述： 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器)
中文描述： 32位RISC嵌入式控制器（32位的RISC結(jié)構(gòu)嵌入式控制器）
文件頁(yè)數(shù)： 56/58頁(yè)
文件大小： 878K
代理商： POWERPC 405GP
PowerPC 405GP Embedded Processor Data Sheet
56
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable default initial
conditions prior to PPC405GP start-up. The actual capture instant is the nearest reference clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. These pins are use for strap functions only during
reset. They are used for other signals during normal operation. The following table lists the strapping pins
along with their functions and strapping options. The pin for the 456-ball package is listed first (for example,
AF3), followed by the corresponding pin for the 413-ball package (for example, U8), which appears as
AF3/U8.
Strapping Pin Assignments
Function
Option
Ball Strapping
PLL Tuning
for 6
≤
M
≤
7 use choice 3
for 7 < M
≤
12 use choice 5
for 12 < M
≤
32 use choice 6
See Note.
AF3/U8
AF2/T8
AD16/AB15
Choice 1; TUNE[5:0] = 010001
0
0
0
Choice 2; TUNE[5:0] = 010010
0
0
1
Choice 3; TUNE[5:0] = 010011
0
1
0
Choice 4; TUNE[5:0] = 010100
0
1
1
Choice 5; TUNE[5:0] = 010101
1
0
0
Choice 6; TUNE[5:0] = 010110
1
0
1
Choice 7; TUNE[5:0] = 010111
1
1
0
Choice 8; TUNE[5:0] = 100100
1
1
1
PLL Forward Divider
D16/A17
B15/B14
Bypass mode
0
0
Divide by 3
0
1
Divide by 4
1
0
Divide by 6
1
1
PLL Feedback Divider
B14/A15
C12/A8
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
PLB Divider from CPU
P25/R23
L24/J22
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
OPB Divider from PLB
L25/K21
J26/F22
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
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