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參數(shù)資料
| 型號： | PowerPC 405GP |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC結(jié)構(gòu)嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC結(jié)構(gòu)嵌入式控制器） |
| 文件頁數(shù)： | 34/58頁 |
| 文件大?。?/td> | 878K |
| 代理商： | POWERPC 405GP |
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PowerPC 405GP Embedded Processor Data Sheet
34
PCIStop
The target of the current PCI transaction can assert PCIStop to
indicate to the requesting PCI master that it wants to end the
current transaction.
I/O
5V tolerant
3.3V PCI
4
PCIDevSel
PCIDevSel is driven by the target of the current PCI transaction. A
PCI target asserts PCIDevSel when it has decoded an address
and command encoding and claims the transaction.
I/O
5V tolerant
3.3V PCI
4
PCIIDSel
PCIIDSel is used during configuration cycles to select the PCI
slave interface for configuration
I
5V tolerant
3.3V PCI Rcvr
5
PCISErr
PCISErr is used for reporting address parity errors or catastrophic
failures detected by a PCI target.
I/O
5V tolerant
3.3V PCI
4
PCIPErr
PCIPErr is used for reporting data parity errors on PCI
transactions. PCIPErr is driven active by the device receiving
PCIAD0:31, PCIC0:3[BE0:3], and PCIParity, two PCI clocks
following the data in which bad parity is detected.
I/O
5V tolerant
3.3V PCI
4
PCIClk
PCIClk is used as the asynchronous PCI clock when in asynch
mode. It is unused when the PCI interface is operated
synchronously with the PLB bus.
I
5V tolerant
3.3V PCI Rcvr
5
PCIReset
PCI specific reset
O
5V tolerant
3.3V PCI
PCIINT[PerWE]
PCI interrupt. Open-drain output (two states; 0 or open circuit)
or
Peripheral write enable. Logical AND of the four PerWBE0:3 write
byte enables
O
5V tolerant
3.3V PCI
PCIReq0[Gnt]
Multipurpose signal, used as PCIReq0 when internal arbiter is
used, and as Gnt when external arbiter is used.
I
5V tolerant
3.3V PCI Rcvr
4
PCIReq1
PCIReq2
PCIReq3
PCIReq4
PCIReq5
Used as PCIReq1:5 input when internal arbiter is used
I
5V tolerant
3.3V PCI Rcvr
4
PCIGnt0[Req]
Gnt0 when internal arbiter is used
or
Req when external arbiter is used
O
5V tolerant
3.3V PCI
PCIGnt1
PCIGnt2
PCIGnt3
PCIGnt4
PCIGnt5
Used as PCIGnt1:5 output when internal arbiter is used.
O
5V tolerant
3.3V PCI
Signal Functional Description
(Part 2 of 12)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k
to 5V
)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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