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PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
362
Configuration 2 register is set to logic 1, as in Figure 62. TGAPCLK remains high
during the overhead bit positions. TDATI is sampled on the falling edge of
TGAPCLK.
Figure 63
- Framer Mode DS3 Receive Output Stream
RDATO[x]
INFO 84
RFPO/RMFPO[x]
INFO 84
INFO 83
INFO 82
X1
INFO 2
INFO 1
X2
INFO 1
INFO 2
INFO 3
INFO 84
INFO 82
INFO 83
F4
INFO 82
INFO 83
ROVRHD[x]
RSCLK[x]
Figure 64
- Framer Mode DS3 Receive Output Stream with RGAPCLK
RGAPCLK[x]
RDATO[x]
INFO 84
INFO 84
INFO 83
INFO 82
INFO 2
INFO 1
INFO 1
INFO 2
INFO 3
INFO 84
INFO 82
INFO 83
INFO 82
INFO 83
INFO 84
The Framer Mode DS3 Receive Output Stream diagrams (Figure 63 and Figure
64) show the format of the outputs RDATO, RFPO/RMFPO, RSCLK (and
RGAPCLK), and ROVRHD when the FRMRONLY bit in the S/UNI-QJET
Configuration 1 register is set. Figure 63 shows the data streams when the
S/UNI-QJET is configured for the DS3 receive format. If the RXMFPO and
8KREFO register bits are logic 0, RFPO is valid and will pulse high for one
RSCLK cycle on first bit of each M-subframe with alignment to the RDATO data
stream. If the RXMFPO register bit is a logic 1 (as shown in Figure 63) and the
8KREFO register bit is logic 0, RMFPO is valid and will pulse high on the X1 bit
of the RDATO data output stream. ROVRHD will be high for every overhead bit
position on the RDATO data stream. As shown in Figure 64 the RGAPCLK
output is available in place of RSCLK when the RXGAPEN bit in the S/UNI-QJET
Configuration 2 register is set to logic 1. RGAPCLK remains high during the
overhead bit positions and RDATO does not change.
Figure 65
- Framer Mode G.751 E3 Transmit Input Stream
TDATI[x]
bit 1536
0
TFPI/TMFPI[x]
Nat
RAI
1
1
1
1
0
1
0
0
bit 1531
bit 1529
bit 1530
bit 1532
bit 1533
bit 1534
bit 1535
TFPO/TMFPO[x]
0
bit13
TICLK[x]