![](http://datasheet.mmic.net.cn/330000/PM7346_datasheet_16444391/PM7346_354.png)
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
333
programming for common repetitive sequences are given below in the Common
Test Patterns section.
For pattern generation, the desired pattern must be written into the PRGD
Pattern Insertion registers. The repetitive pattern will then be continuously
generated. The generated pattern will be inserted in the output data stream, but
the phase of the pattern cannot be guaranteed.
For pattern detection, the PRGD will determine if a repetitive pattern of the
length specified in the pattern length register exists in the input stream. It does
so by loading the first N bits from the data stream, and then monitoring to see if
the pattern loaded repeats itself error free for the subsequent 48 bit periods. It
will repeat this process until it finds a repetitive pattern of length N, at which point
it begins counting errors (and possibly re-synchronizing) in the same way as for
pseudo-random sequences. Note that the PRGD does NOT look for the pattern
loaded into the Pattern Insertion registers, but rather automatically detects any
repetitive pattern of the specified length. The precise pattern detected can be
determined by initiating a PRGD update, setting PDR[1:0] = 00 in the PRGD
Control register, and reading the Pattern Detector registers (which will then
contain the 32 bits detected immediately prior to the strobe).
12.14.2
Common Test Patterns
The PRGD can be configured to monitor the standardized pseudo random and
repetitive patterns described in ITU-T O.151. The register configurations
required to generate these patterns and others are indicated in the two tables
below:
Table 37
- Pseudo Random Pattern Generation (PS bit = 0)
Pattern Type
TR
LR
IR#1
IR#2
IR#3
IR#4
TINV
RINV
23 -1
00
02
FF
FF
FF
FF
0
0
24 -1
00
03
FF
FF
FF
FF
0
0
25-1
01
04
FF
FF
FF
FF
0
0
26 -1
04
05
FF
FF
FF
FF
0
0
27 -1
00
06
FF
FF
FF
FF
0
0
27 -1 (Fractional T1 LB
Activate)
03
06
FF
FF
FF
FF
0
0